Computer Architecture Pipeline with Bypass-Signals: Timing and Signal Paths, Exercises of Computer Architecture and Organization

Computer Architecture HW #2

1. You are to assume the same 6-stage pipeline discussed in class (and textbook) when answering these questions.

Assume that the first register in an arithmetic operation is the destination register, e.g., in “ADD R3, R2, R1”

register R3 receives the result of adding registers R2 and R1.

a. What would the timing be without bypass-signal paths/forwarding (use “stalls” to solve the data hazard)?

(This code might require more or less that 15 cycles)

SUB R2, R3, R4

ADD R7, R6, R9

MUL R6, R1, R8

Time d

(Assume that a register cannot be written and the new value read in the same stage.)

b. What would the timing be with bypass-signal paths?

(This code might require more that 15 cycles)

SUB R2, R3, R4

ADD R7, R6, R9

MUL R6, R1, R8

LOAD R1, 4(R5)

SUB R5, R3, R4

LOAD R4, 16(R3)

(Assume that a register cannot be written and the new value read in the same stage.)