Assignment 8
Computer Science 240
Fall 2008
Due: Monday, November 17
Reading. Patterson and Hennessy §5.1 -- §5.4, §A.9, §A.10
8.1. Exercises 5.1, 5.2, and 5.3 in the text help you learn yet another set of terminology
and signal name helpers. Complete each exercise.
8.2. Suppose we have a floating-point unit that requires 400 ps for a floating-point add
and 600 ps for a floating-point multiply, not including the time to get the instruction or
read and write any registers, which take the same as for an integer instruction. Use the
functional unit times from the example on page 315. In these exercises, we will find the
performance ratio between an implementation
in which the clock cycle is different for each instruction class and an implementa-
tion in which all instructions have the same clock cycle time. Assume the following:
• All loads take the same time and comprise 30% of the instructions.
• All stores take the same time and comprise 15% of the instructions.
• R-format instructions comprise 25% of the mix.
• Branches comprise 10% of the instructions, while jumps comprise 5%.
• FP add and subtract take the same time and together total 5% of the instructions.
• FP multiply and divide take the same time and together total 10% of the
instructions.
Find the time for the FP instructions.
8.3. For the datapath and instruction mix the previous exercise find the time for the
processor with a single clock cycle length equal to the longest instruction.
8.4. For the datapath and instruction mix as in the previous exercise, find the time for
the processor with a varying-length clock.
8.5. We wish to add the instruction sll (shift left logical) which is described in Section
2.5 to the single-cycle datapath described in Chapter 5 of the text. Add any necessary
datapaths and control signals to the single-cycle datapath of Figure 5.17 on page 307 of
the text and show the necessary addition to Figure 5.18 on page 308. You can photocopy
these figures to make it faster to show the additions.
