Multi-Cycle Processor - Computer Architecture - Lecture Slides, Slides of Computer Science

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CPSC 321

Computer Architecture and Engineering

Lecture 7

Designing a Multi-cycle Processor

Recap: A Single Cycle Datapath

ALUctr

Clk

busW

RegWr

busA

busB

Rw Ra Rb 32 32-bit Registers

Rs

Rt

Rt

Rd RegDst

Extender

Mux

Mux

imm16 16 32

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data In

WrEn 32

Adr Data Memory

MemWr ALU

Instruction Fetch Unit Clk

Equal

Instruction<31:0>

Rs Rt Rd Imm

nPC_sel

The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

° Today’s Topic: Designing the Datapath for the

Multiple Clock Cycle Datapath

Control

Datapath

Memory

Processor Input

Output

Abstract View of our single cycle processor

° looks like a FSM with PC as state

PC

Next PC^ Register

Fetch

ALU Reg. Wrt

Mem Access

DataMem

Instruction

Fetch

Result Store

ALUctr

RegDst

ALUSrc ExtOp^ MemWr

Equal nPC_sel^ MemRd^ MemWr^ RegWr

Main

Control

ALU

control

op

fun

Ext

Reducing Cycle Time

° Cut combinational dependency graph and insert register / latch

° Do same work in two fast cycles, rather than one slow one

° May be able to short-circuit path and remove some components

for some instructions!

storage element

Acyclic

Combinational

Logic

storage element

storage element

Acyclic

Combinational

Logic (A)

storage element

storage element

Acyclic

Combinational

Logic (B)

Basic Limits on Cycle Time

° Next address logic

• PC <= branch? PC + offset : PC + 4

° Instruction Fetch

• InstructionReg <= Mem[PC]

° Register Access

• A <= R[rs]

° ALU operation

• R <= A + B

PC

Next PC^ Operand

Fetch

Exec Reg.File

MemAccess

DataMem

Instruction

Fetch

Result Store

ALUctr

RegDst ExtOp^ ALUSrc nPC_sel^ MemRd^ MemWr^ RegWr^ MemWr

Control

Example Multicycle Datapath

° Critical Path?

PC

Next PC

Operand

Fetch

Instruction

Fetch

nPC_sel

IR

Reg

File^ ExtALU

Reg.File

Mem Acces

s

DataMem

Result Store

MemRd MemWr^ RegDst^ RegWr

S

M

Equal MemToReg

ExtOp^ ALUSrc^ ALUctr

A

B

E

Recall: Step-by-step Processor Design

Step 1: ISA => Logical Register Transfers

Step 2: Components of the Datapath

Step 3: RTL + Components => Datapath

Step 4: Datapath + Logical RTs => Physical RTs

Step 5: Physical RTs => Control

Step 4: Logical immed

° Logical Register Transfer

° Physical Register Transfers

inst Logical Register Transfers

ORI R[rt] <– R[rs] OR ZExt(Im16); PC <– PC + 4

inst Physical Register Transfers IR <– MEM[pc] ORI A<– R[rs]; B <– R[rt] S <– A or ZExt(Im16) R[rt] <– S; PC <– PC + 4

Exec

Reg.File

Mem Acces

s

DataMem

S

M

PC^ RegFile

Next PC

IR

Inst. Mem

Time

A

B

E

Step 4 : Load

° Logical Register Transfer

° Physical Register Transfers

inst Logical Register Transfers

LW R[rt] <– MEM[R[rs] + SExt(Im16)];

PC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] LW A<– R[rs]; B <– R[rt] S <– A + SExt(Im16) M <– MEM[S] R[rd] <– M; PC <– PC + 4

Exec

Reg.File

MemAcces

s

DataMem

S

M

PC^ RegFile

Next PC

IR

Inst. Mem

A

B

E

Time

Step 4 : Branch

° Logical Register Transfer

° Physical Register Transfers

inst Logical Register Transfers

BEQ if R[rs] == R[rt]

then PC <= PC + 4+SExt(Im16) || 00

else PC <= PC + 4

Exec

Reg.File

MemAcces

s

DataMem

S

M

PC^ RegFile

Next PC

IR

Inst. Mem

inst Physical Register Transfers IR <– MEM[pc] BEQ E<– (R[rs] = R[rt]) if !E then PC <– PC + 4 else PC <– PC+4+SExt(Im16)||

A

B

E

Time

Alternative data-path (book): Multiple Cycle Datapath

° Minimizes Hardware: 1 memory, 1 adder

Ideal Memory WrAdr Din

RAdr

32 32

32 Dout

MemWr 32

ALU

32

32

ALUOp

ALU

Control

Instruction Reg

32

IRWr

32

Reg File

Ra

Rw busW

Rb 5

5

32

busA

busB 32

RegWr

Rs

Rt

Mux^0

1

Rt

Rd

PCWr

ALUSelA

1^ Mux^ 0

RegDst

Mux^0

1

32

PC

MemtoReg

Extend

ExtOp

Mux^0

1

32

0 1 2 3

Imm (^1632)

ALUSelB

Mux^1

0

Target 32

Zero

Zero

PCWrCond PCSrc BrWr

32

IorD

ALU Out

Step 4 ⇒ Control Specification for multicycle proc

IR <= MEM[PC]

R-type

A <= R[rs] B <= R[rt]

S <= A fun B

R[rd] <= S PC <= PC + 4

S <= A or ZX

R[rt] <= S PC <= PC + 4

ORi

S <= A + SX

R[rt] <= M PC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= B

PC <= PC + 4

BEQ

PC <=

Next(PC,Equal)

SW

“instruction fetch”

“decode / operand fetch”

Execute

Memory

Write-back

Traditional FSM Controller

State

next

State

op

Equal

control points

state op cond

next

state control points

Truth Table

datapath State