Download MIPS Instruction Set: Integer Operate and Branch Instructions and more Assignments Computer Architecture and Organization in PDF only on Docsity!
ECE 412 Instruction Set Architecture Description
Matt Frank
September 20, 2003
This document describes the assembly programmer’s interface to the processor we are using in ECE
- The architecture is similar, but not identical to, the MIPS R4000. The major differences are
- Floating point:
(a) Floating point operations use the same register file as integer operations. (b) All floating point operations are single precision. (c) Floating point compares have a destination register instead of setting a flag. (d) The floating point branches, BC1T and BC1F, are removed, since the integer versions have equiv- alent functionality. (e) Floating point divide uses the FD register implicitly instead of an explicit destination register. (f) The only available floating point rounding mode is round-to-nearest even.
- Instead of a single multiply instruction, there are three low-latency instructions, MULH, MULHU and MULL, which place their results in a GPR instead of HI/LO.
- The instruction set and encodings are slightly different. See below for more details.
- Because of jump instruction encodings, only the low 256Kbytes (64Kwords) of memory is usable to hold instructions.
- The memory operations are little endian. In other words, if there is a word stored at address P, then the low order byte is stored at address P and the most significant byte is stored at address P+3. For reference, SPARC is big endian and x86 is little endian.
- All multi-cycle operations (branches, loads, multiplies, divides) are fully interlocked. There are no delay slots.
1 Data types
The processor supports two data types, unsigned 32 bit integers and 32 bit IEEE floating point numbers. When signed integers are required they are represented in 2s-complement. IEEE single precision floating point format represents data as follows:
s
31 exp
30 23
mantissa
22 0
In general the number represented by a particular bit pattern is given by:
mantissa exp ^
The floating point number 0 is represented by the bit pattern 0.
2 Registers
The processor state consists of the program counter, 32 general purpose registers, called, “$0” through “$31,” two registers that are used for the results of integer division, “$lo” and “$hi”, and one register used for the result of floating point division, “$fd.” The general purpose registers are used for all integer and floating point operations, there is no separate floating point register file. Register $0 always contains the value 0. Register $31 is used to save the return value for jump-and-link instructions. Several other registers are managed in particular ways by the compiler:
register alias use $0 Always has value zero. $1 $at Reserved for the assembler. $2 - $3 Expresssion evaluation and procedure return values. $4 - $7 Used to pass first 4 words of actual arguments. Not preserved across procedure calls. $8 - $15 Temporaries. Not preserved across procedure calls. $16 - $23 Callee saved registers. $24 - $27 Unused by compiler. $28 $gp Global pointer. (Set to 0 by our software). $29 $sp The stack pointer. $30 A callee saved register, sometimes used by gcc as a frame pointer. $31 $ra The link register
3 Instruction encodings
All instructions are 32 bit. Each instruction starts with a 5 bit primary opcode. The “p” bit can be used as a hint to the branch predictor. It is set true by the assembler for backward branches, and false otherwise.
opcode
31 27 p
26 25 0
3.1 Primary opcode table
This map is for the first five bits of the instruction (the “opcode” field). It is used for instructions that require 2 registers and a 16 bit immediate field.
opcode
31 27 p
26
rs
25 21
rt
20 16
immediate
15 0
instr[29:27] 2 000 001 010 011 100 101 110 111 00 SPECIAL REGIMM BEQ BNE instr 01 ADDIU SLTI SLTIU ANDI ORI XORI AUI [31:30] 10 LB LH LW LBU LHU FPU 11 SB SH SW COM
instr[2:0] 2 000 001 010 011 100 101 110 111 000 ADD.S SUB.S MUL.S DIV.S ABS.S NEG.S 001 TRUNC.S 010 instr 011 [5:3] 100 CVT.S CVT.W 101 110 C.EQ.S 111 C.LT.S C.LE.S
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
COM
5 0
instr[2:0] 2 000 001 010 011 100 101 110 111 000 001 UNIX HALT 010 instr 011 [5:3] 100 101 110 111
4 Instruction descriptions
4.1 Integer operate instructions
4.1.1 ADDIU
Encoding
(^31 )
0
26
rs
(^25 )
rt
20 16
immediate
15 0
Assembly syntax addiu $rt, $rs, immediate
Description Add immediate unsigned. The immediate field is sign extended, added to the value in reg- ister rs and the result placed in register rt.
RTL Reg[rt] := Reg[rs] + sign_ext(imm)
4.1.2 ADDU
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
100001
5 0
Assembly syntax addu $rd, $rs, $rt
Description Add unsigned. The values in registers rs and rt are added and the result is placed in register rd.
RTL Reg[rd] := Reg[rs] + Reg[rt]
4.1.3 AND
Encoding
31 27
0
26
rs
25 21
rt
20 16
rd
15 11
00000
6 10
100100
5 0
Assembly syntax and $rd, $rs, $rt
Description And. The values in registers rs and rt are bitwise anded and the result is placed in register rd.
RTL Reg[rd] := Reg[rs] & Reg[rt]
4.1.4 ANDI
Encoding
31 27
0
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax andi $rt, $rs, immediate
Description Add immediate unsigned. The immediate field is zero extended, bitwise anded with the value in register rs and the result placed in register rt.
RTL Reg[rt] := Reg[rs] & zero_ext(imm)
4.1.5 AUI
Encoding
31 27
0
26
rs
25 21
rt
20 16
immediate
15 0
Assembly syntax aui $rt, $rs, immediate
Description Add upper immediate. The immediate field is shifted left 16 bits and added to the value in register rs. The result is placed in register rt.
RTL Reg[rt] := Reg[rs] + (imm << 16)
Assembly syntax mffd $rd
Description Move from FD. The contents of the FD register (floating point divide result) are moved to register rd.
RTL Reg[rd] := Reg[FD]
4.1.10 MFHI
Encoding
31 27
0
26
00000
25 21
00000
20 16
rd
15 11
00000
6 10
010000
5 0
Assembly syntax mfhi $rd
Description Move from HI. The contents of the HI register (remainder of integer divide result) are moved to register rd.
RTL Reg[rd] := Reg[HI]
4.1.11 MFLO
Encoding
31 27
0
26
00000
25 21
00000
20 16
rd
15 11
00000
6 10
010010
5 0
Assembly syntax mflo $rd
Description Move from LO. The contents of the LO register (integer division result) are moved to register rd.
RTL Reg[rd] := Reg[LO]
4.1.12 MTFD
Encoding
31 27
0
26
rs
25 21
00000
20 16
00000
15 11
00000
6 10
010101
5 0
Assembly syntax mtfd $rs
Description Move to FD. The contents of register rs are moved to the FD register.
RTL Reg[FD] := Reg[rs]
4.1.13 MTHI
Encoding
31 27
0
26 rs
25 21
00000
20 16
00000
15 11
00000
6 10
010001
5 0
Assembly syntax mthi $rs
Description Move to HI. The contents of register rs are moved to the HI register.
RTL Reg[HI] := Reg[rs]
4.1.14 MTLO
Encoding
31 27
0
26 rs
25 21
00000
20 16
00000
15 11
00000
6 10
010011
5 0
Assembly syntax mtlo $rs
Description Move to LO. The contents of register rs are moved to the LO register.
RTL Reg[LO] := Reg[rs]
4.1.15 MULH
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
101000
5 0
Assembly syntax mulh $rd, $rs, $rt
Description Multiply high. The values in registers rs and rt are multiplied as signed 2s-complement integers to produce a 64 bit result. The high 32 bits of this result is placed in register rd.
RTL Reg[rd] := (Reg[rs] *s Reg[rt])63:
4.1.16 MULHU
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
101001
5 0
Assembly syntax mulhu $rd, $rs, $rt
Description Multiply high unsigned. The values in registers rs and rt are multiplied as unsigned integers to produce a 64 bit result. The high 32 bits of this result is placed in register rd.
Assembly syntax ori $rt, $rs, immediate
Description Or immediate. The immediate field is zero extended, bitwise ored with the value in register rs and the result placed in register rt.
RTL Reg[rt] := Reg[rs] | zero_ext(imm)
4.1.21 RAND
Encoding
31 27
0
26
rs
25 21
rt
20 16
rd
15 11
00000
6 10
110000
5 0
Assembly syntax rand $rd
Description Random. A pseudorandomly generated 32 bit integer is placed in register rd.
RTL Reg[rd] := mrand48()
4.1.22 SLL
Encoding
31 27
0
26
00000
25 21
rt
20 16
rd
15 11
shamt
6 10
000000
5 0
Assembly syntax sll $rt, $rs, shamt
Description Shift left logical. The value in registers rt is shifted left by the number of bits specified in the shamt field. The result is placed in register rd.
RTL Reg[rd] := Reg[rt] << shamt
4.1.23 SLLV
Encoding
31 27
0
26
rs
25 21
rt
20 16
rd
15 11
00000
6 10
000100
5 0
Assembly syntax sllv $rd, $rs, $rt
Description Shift left logical variable. The value in registers rt is shifted left by the number of bits speci- fied in register rs. The result is placed in register rd.
RTL Reg[rd] := Reg[rt] << (Reg[rs] & 111112 )
4.1.24 SLT
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
101010
5 0
Assembly syntax slt $rd, $rs, $rt
Description Set less than. The values in registers rs and rt are compared as signed values. If rs is less than rt, then a 1 is placed in register rd, else a 0 is placed in register rd.
RTL Reg[rd] := if (Reg[rs] <s Reg[rt]) then 1 else 0
4.1.25 SLTI
Encoding
31 27
0
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax slti $rt, $rs, immediate
Description Set less than immediate. The value in rs is compared as a signed value to the sign extended immediate. If rs is less than the immediate then a 1 is placed in register rt, else a 0 is placed in register rt.
RTL Reg[rt] := if (Reg[rs] <s sign_ext(imm)) then 1 else 0
4.1.26 SLTIU
Encoding
31 27
0
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax sltiu $rt, $rs, immediate
Description Set less than immediate unsigned. The value in rs is compared as an unsigned value to the sign extended immediate. If rs is less than the immediate then a 1 is placed in register rt, else a 0 is placed in register rt.
RTL Reg[rt] := if (Reg[rs] <u sign_ext(imm)) then 1 else 0
4.1.27 SLTU
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
101011
5 0
Assembly syntax sltu $rd, $rs, $rt
4.1.31 SRLV
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
000110
5 0
Assembly syntax srlv $rd, $rs, $rt
Description Shift right logical variable. The value in registers rt is shifted right logically by the number of bits specified in register rs. The result is placed in register rd.
RTL Reg[rd] := Reg[rt] >>u (Reg[rs] & 111112 )
4.1.32 SUBU
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
100011
5 0
Assembly syntax subu $rd, $rs, $rt
Description Subtract unsigned. The value in register rt is subtracted from the value in register rs and the result is placed in register rd.
RTL Reg[rd] := Reg[rs] - Reg[rt]
4.1.33 XOR
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
100110
5 0
Assembly syntax xor $rd, $rs, $rt
Description Xor. The values in register rs and rt are bitwise exclusive-ored and the result is placed in register rd.
RTL Reg[rd] := Reg[rs] ˆ Reg[rt]
4.1.34 XORI
Encoding
31 27
0
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax xori $rt, $rs, immediate
Description Xor immediate. The immediate field is zero extended, bitwise exclusive-ored with the value in register rs and the result placed in register rt.
RTL Reg[rt] := Reg[rs] ˆ zero_ext(imm)
4.2 Branch instructions
4.2.1 BEQ
Encoding
31 27 p
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax beq $rs, $rt, immediate
Description Branch equal. If the value in register rs is equal to the value in register rt, then the program counter is changed by the signed amount given in the immediate field.
RTL
program_counter := if (Reg[rs] == Reg[rt]) then program_counter + (sign_ext(imm) * 4) else program_counter + 4
4.2.2 BGEZ
Encoding
31 27 p
26 rs
25 21
00010
20 16
immediate
15 0
Assembly syntax bgez $rs, immediate
Description Branch greater than or equal to zero. If the value in register rs is greater than or equal to zero (its high bit is unset), then the program counter is changed by the signed amount given in the immediate field.
RTL
program_counter := if (Reg[rs] >= 0) then program_counter + (sign_ext(imm) * 4) else program_counter + 4
4.2.3 BGEZAL
Encoding
(^31 ) p
26
rs
(^25 )
10010
20 16
immediate
15 0
Assembly syntax bgezal $rs, immediate
Assembly syntax bltz $rs, immediate
Description Branch less than zero. If the value in register rs is less than zero, then the program counter is changed by the signed amount given in the immediate field.
RTL
program_counter := if (Reg[rs] < 0) then program_counter + (sign_ext(imm) * 4) else program_counter + 4
4.2.7 BLTZAL
Encoding
31 27 p
26 rs
25 21
10000
20 16
immediate
15 0
Assembly syntax bltzal $rs, immediate
Description Branch less than zero and link. Uncondiationally the program counter + 4 is placed in the link register. If the value in register rs is less than zero, then the program counter is changed by the signed amount given in the immediate field.
RTL
Reg[31] := program_counter + 4 program_counter := if (Reg[rs] < 0) then program_counter + (sign_ext(imm) * 4) else program_counter + 4
4.2.8 BNE
Encoding
31 27 p
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax bne $rs, $rt, immediate
Description Branch not equal. If the value in register rs is not equal to the value in register rt, then the program counter is changed by the signed amount given in the immediate field.
RTL
program_counter := if (Reg[rs] != Reg[rt]) then program_counter + (sign_ext(imm) * 4) else program_counter + 4
4.2.9 J
Encoding
31 27 p
26 rs
25 21
11000
20 16
immediate
15 0
Assembly syntax j immediate
Description Jump. Control jumps to the indicated address.
RTL program_counter := zero_ext(imm) * 4
4.2.10 JAL
Encoding
31 27 p
26 rs
25 21
11001
20 16
immediate
15 0
Assembly syntax jal immediate
Description Jump and link. Uncondiationally the program counter + 4 is placed in the link register. The program counter jumps to the address indicated by the immediate field.
RTL
Reg[31] := program_counter + 4 program_counter := zero_ext(imm) * 4
4.2.11 JR
Encoding
31 27
0
26
rs
25 21
00000
20 16
00000
15 11
00000
6 10
001000
5 0
Assembly syntax jr $rs
Description Jump register. Control jumps to the address given in register rs.
RTL program_counter := Reg[rs]
4.2.12 JALR
Encoding
31 27
0
26 rs
25 21
00000
20 16
00000
15 11
00000
6 10
001001
5 0
Assembly syntax jalr $rs
4.3.4 LHU
Encoding
31 27 p
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax lhu $rt, $rs(immediate)
Description Load halfword unsigned. The 16 bit halfword at the memory address given by register rs offset by the immediate value is zero extended to 32 bits and loaded into register rt. The computed address must be aligned on a 2 byte boundary.
RTL Reg[rt] = zero_ext(Mem[Reg[rs] + sign_ext(imm)])
4.3.5 LW
Encoding
(^31 ) p
26
rs
(^25 )
rt
20 16
immediate
15 0
Assembly syntax lw $rt, $rs(immediate)
Description Load word. The 32 bit word at the memory address given by register rs offset by the imme- diate value is sign extended to 32 bits and loaded into register rt. The computed address must be aligned on a word boundary.
RTL Reg[rt] = Mem[Reg[rs] + sign_ext(imm)]
4.3.6 SB
Encoding
31 27 p
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax sb $rt, $rs(immediate)
Description Store byte. The low order 8 bit byte of register rt is stored at the memory address given by register rs offset by the immediate value.
RTL Mem[Reg[rs] + sign_ext(imm)] = Reg[rt]7:
4.3.7 SH
Encoding
31 27 p
26 rs
25 21
rt
20 16
immediate
15 0
Assembly syntax sh $rt, $rs(immediate)
Description Store halfword. The low order 16 bit halfword of register rt is stored at the memory address given by register rs offset by the immediate value. The computed address must be aligned on a 2 byte boundary.
RTL Mem[Reg[rs] + sign_ext(imm)] = Reg[rt]15:
4.3.8 SW
Encoding
31 27 p
26
rs
25 21
rt
20 16
immediate
15 0
Assembly syntax sw $rt, $rs(immediate)
Description Store word. The 32 bit word in register rt is stored at the memory address given by register rs offset by the immediate value. The computed address must be aligned on a word boundary.
RTL Mem[Reg[rs] + sign_ext(imm)] = Reg[rt]15:
4.4 Floating point operate instructions
4.4.1 ADD.S
Encoding
31 27
0
26 rs
25 21
rt
20 16
rd
15 11
00000
6 10
000000
5 0
Assembly syntax add.s $rd, $rs, $rt
Description Add single precision floating point. The values in registers rs and rt are added and the result is placed in register rd.
RTL Reg[rd] := Reg[rs] +f Reg[rt]
4.4.2 SUB.S
Encoding
31 27
0
26
rs
25 21
rt
20 16
rd
15 11
00001
6 10
000000
5 0
Assembly syntax sub.s $rd, $rs, $rt
Description Subtract single precision floating point. The values in registers rs and rt are subtracted and the result is placed in register rd.
