VHDL Programming Styles: Structural, Dataflow, and Behavioral - ECGR2181 Homework #7, Assignments of Electrical and Electronics Engineering

Instructions for unc charlotte ecgr2181 students to write three files of vhdl code representing the structural, dataflow, and behavioral programming styles for a 2 to 4 decoder. The characteristics of each style and provides an example filename and comment format.

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Pre 2010

Uploaded on 07/28/2009

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UNC Charlotte - ECGR2181 - Homework #7 - Due 3/16/06
As mentioned in the slides there are three types of VHDL programming styles:
1. Structural (decode2to4_struct.vhd)
Define explicit components and the connections between them.
Textual equivalent of drawing a schematic
2. Dataflow (decode2to4_data.vhd)
Assign expressions to signals
Includes “when” and “select” (case) statements
3. Behavioral (decode2to4_behav.vhd)
Write an algorithm that describes the circuit’s output
May not be synthesizable or may lead to a very large circuit
Primarily used for simulation
Write three files of VHDL code which represent these styles. All three should be of the 2 to 4 decoder
in notes page 5-13. The files should be complete and ready to use in the Xillinx ISE
application. The filenames will be as listed above. The first two lines will be comments that
should look like the following (with your names in it and the correct file name).
// ECGR2181 Homework 6 – filename: decode2to4_struct.vhd
// Student’s name - 3/16/06

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UNC Charlotte - ECGR2181 - Homework #7 - Due 3/16/

As mentioned in the slides there are three types of VHDL programming styles:

  1. Structural (decode2to4_struct.vhd)
    • Define explicit components and the connections between them.
    • Textual equivalent of drawing a schematic
  2. Dataflow (decode2to4_data.vhd)
    • Assign expressions to signals
    • Includes “when” and “select” (case) statements
  3. Behavioral (decode2to4_behav.vhd)
    • Write an algorithm that describes the circuit’s output
    • May not be synthesizable or may lead to a very large circuit
    • Primarily used for simulation

Write three files of VHDL code which represent these styles. All three should be of the 2 to 4 decoder in notes page 5-13. The files should be complete and ready to use in the Xillinx ISE application. The filenames will be as listed above. The first two lines will be comments that should look like the following (with your names in it and the correct file name).

// ECGR2181 Homework 6 – filename: decode2to4_struct.vhd // Student’s name - 3/16/