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Dataflow Modeling
- Dataflow modeling uses a number of operators that act on
operands to produce desired results.
- Verilog HDL provides about 30 operator types.
- Dataflow modeling uses continuous assignments and the
keyword assign.
- A continuous assignment is a statement that assigns a value to
a net.
- The value assigned to the net is specified by an expression
that uses operands and operators.
Dataflow Modeling (2)
//Dataflow description of a 2-to-4-line decoder module decoder_df (A,B,E,D); input A,B,E; output [0:3] D; assign D[0] = ~(~A & ~B & ~E), D[1] = ~(~A & B & ~E), D[2] = ~(A & ~B & ~E), D[3] = ~(A & B & ~E); endmodule
A 2-to-1 line multiplexer with data inputs A and B, select input S, and output Y is described with the continuous assignment
assign Y = (A & S) | (B & ~S)
Dataflow Modeling (4)
- The addition logic of 4 bit adder is described by a single
statement using the operators of addition and concatenation.
- The plus symbol (+) specifies the binary addition of the 4 bits
of A with the 4 bits of B and the one bit of Cin.
- The target output is the concatenation of the output carry
Cout and the four bits of SUM.
- Concatenation of operands is expressed within braces and a
comma separating the operands. Thus, { Cout,SUM }
represents the 5-bit result of the addition operation.
Dataflow Modeling (5)
- Dataflow Modeling provides the means of describing combinational circuits by their function rather than by their gate structure.
- Conditional operator (?:)
condition? true-expression : false-expression;
- A 2-to-1 line multiplexer assign OUT = select? A : B;
//Dataflow description of 2-to-1-line mux module mux2x1_df (A,B,select,OUT); input A,B,select; output OUT; assign OUT = select? A : B; endmodule
Behavioral Modeling (2)
- The procedural assignment statements inside the always block are executed every time there is a change in any of the variable listed after the @ symbol. (Note that there is no “;” at the end of always statement)
//Behavioral description of 2-to-1-line multiplexer module mux2x1_bh(A,B,select,OUT); input A,B,select; output OUT; reg OUT; always @ (select or A or B) if (select == 1) OUT = A; else OUT = B; endmodule
Behavioral Modeling (3)
4-to-1 line
multiplexer
Behavioral Modeling (5)
• In 4-to-1 line multiplexer, the select input is defined
as a 2-bit vector and output y is declared as a reg
data.
• The always block has a sequential block enclosed
between the keywords case and endcase.
• The block is executed whenever any of the inputs
listed after the @ symbol changes in value.
Writing a Test Bench
- A test bench is an HDL program used for applying stimulus to
an HDL design in order to test it and observe its response
during simulation.
- In addition to the always statement, test benches use the
initial statement to provide a stimulus to the circuit
under test.
- The always statement executes repeatedly in a loop. The
initial statement executes only once starting from simulation
time=0 and may continue with any operations that are
delayed by a given number of units as specified by the symbol
Writing a Test Bench (2)
• Inputs to a 3-bit truth table can be generated
with the initial block
initial begin
D = 3’b000; repeat (7); #10 D = D + 3’b001;
end
• The 3-bit vector D is initialized to 000 at time=0.
The keyword repeat specifies looping
statement: one is added to D seven times, once
every 10 time units.
Writing a Test-Bench (3)
- A stimulus module is an HDL program that has the following form. module testname Declare local reg and wire identifiers Instantiate the design module under test. Generate stimulus using initial and always statements Display the output response. endmodule
- A test module typically has no inputs or outputs.
- The signals that are applied as inputs to the design module for simulation are declared in the stimulus module as local reg data type.
- The outputs of the design module that are displayed for testing are declared in the stimulus model as local wire data type.
- The module under test is then instantiated using the local identifiers.
Writing a Test-Bench (5)
- The response to the stimulus generated by the initial and always blocks will appear at the output of the simulator as timing diagrams.
- It is also possible to display numerical outputs using Verilog system tasks.
- $display – display one-time value of variables or strings with end-of-line return,
- $write – same $display but without going to next line.
- $monitor – display variables whenever a value changes during simulation run.
- $time – displays simulation time
- $finish – terminates the simulation
- The syntax for $display,$write and $monitor is of the form Task-name (format-specification, argument list); E.g. $display (%d %b %b, C,A,B); $display (“time = %0d A = %b B=%b”, $time ,A,B);
Writing a Test-Bench (6)
//Stimulus for mux2x1_df module testmux; reg TA,TB,TS; //inputs for mux wire Y; //output from mux mux2x1_df mx (TA,TB,TS,Y); // instantiate mux initial begin $monitor( ”select=%b A=%b B=%b OUT=%b",TS,TA,TB,Y); TS = 1; TA = 0; TB = 1; #10 TA = 1; TB = 0; #10 TS = 0; #10 TA = 0; TB = 1; end endmodule
Descriptions of Circuits
- Structural Description – This is directly equivalent to the
schematic of a circuit and is specifically oriented to describing
hardware structures using the components of a circuit.
- Dataflow Description – This describes a circuit in terms of
function rather than structure and is made up of concurrent
assignment statements or their equivalent. Concurrent
assignments statements are executed concurrently, i.e. in
parallel whenever one of the values on the right hand side of
the statement changes.
Descriptions of Circuits (2)
- Hierarchical Description – Descriptions that represent circuits
using hierarchy have multiple entities, one for each element
of the Hierarchy.
- Behavioral Description – This refers to a description of a
circuit at a level higher than the logic level. This type of
description is also referred to as the register transfers level.
