Asynchronous Machine Design: Memory & Robot Controller - Prof. Janak H. Patel, Lab Reports of Electrical and Electronics Engineering

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ECE

DIGITAL SYSTEMS LABORATORY

© Janak H. Patel Department of Electrical and Computer Engineering^ University of Illinois at Urbana-Champaign

Experiment 5Asynchronous MachineDesign

Today’s Topics

z^ Revisit Experiment 4 (due this week)^ „^ Shift Register Memory^ „^ RAM with error detection z^ Experiment 5 (due next week) z^ Asynchronous Machine Design z^ Critical Race and State Encoding z^ Experiment 5 state table

Experiment 5

z^ Asynchronous Robot Platform Controller^ „^ Three

control inputs and

six^ outputs

„^ Design using only gates and latches „^ No flip-flops or clocks permitted in design „^ You can assume that only one input changes atone time and the second change will not occur untilthe circuit outputs are stabilized „^ Outputs must be glitch-free „^ TASKS^ ‹^ Develop a symbolic State Table^ ‹^ Assign Binary Encoding to States to prevent Races^ ‹^ Develop Latch-input equations from the table

Fundamental Mode Asynch Ckts z^ Fundamental Mode

Sequential Circuit

„^ Only one input is allowed to change at one time z Stable State

for an input combination

„^ It is the state for which the next state is itself for thegiven input combination. z Races^ in Asynchronous Circuits^ ‹^ When the next state of a state has an encoding thathas more than one latch output changing, it is calleda^ Race.^ ‹^ For example, for Present State <0110> and theNext State <0000>, the transition may go throughintermediate states <0100>, or <0010>. If theintermediate states lead to an unintended next state

then we call it a

Critical Race

Machine Specification Previous Input^

Current Input

Output

-^

All Switches down

Halt

All Switches down

Left

switch up

Go Straight

All Switches down

Right

switch up

Go Straight

All Switches down

Spin

switch up

Turn 180

Left^ switch up

Left, Right

both up^

Turn Left

Right^ switch up

Left, Right

both up^

Turn Right

Left|Right|Spin up

(Left or Right)& Spin

Stop/Error

(Moore) Partial State Diagram-1^ HALT

TurnLeft L go-str

TurnRight

Spin^180

L^

LR

R

RL

S

L

Not L

R

Not R Not S

Inputs L: Left R: Right S: Spin

Rgo-str Moore Machine

: Output is assigned to the State

• Output is a function of State Variables only - Output does not depend on the Inputs

R L

(Moore) Partial State Diagram-2^ HALT

TurnLeft Lgo-str

TurnRight

Spin^180

L^

LR

R

RL

S

LRS RLS^ Stop/Error

LS or RS

LS

R^ RS

go-str

errorrecovery L R S

Complete State Diagram HALT^

TurnLeft Lgo-str

TurnRight

Spin^180

LRS^000000

100111 111 Stop/Error

010 101, 011^001

ErrorRecovery (^101011) Rgo-str

A B

D C

G F

E

Example of Critical Race

Input Combinations L,R,S Encoding: State

^000

010 100

110 101

Output 011 111

000 : A^ A^

B^ C^

D^ -^

-^ -^ -^ HALT

001 : B^ A^

B^ -^

-^ -^ E^ E^ -^ SPIN

010 : C^ A^

-^ C^ -^ F^ -^ E^ -^ GO STR

011 : D^ A^

-^ -^ D^ G^

E^ -^

-^ GO STR

111 : E^ -^

B^ C^

D^ E^

E^ E^

E^ ERROR

100 : F^ -^

-^ C^ D^ F^ -^ -^ E

RIGHT

110 : G^ -^

-^ C^ D^ G^ -^ -^ E

LEFT Next State

Intended Transition (State

,Input1)^ Æ^

(State2,Input2) may end up in (State

, Input2)

Transition (010:C

,010)^ Æ^ (100:F

,110) is a Critical Race. May end up in (110:G

,110)

Transition (011:D

,100)^ Æ^ (110:G

,110) is a Critical Race. May end up in (111:E

,110)

(There are 8! = 40,320 different state encodings possible for this state table using three state variables)

State Encoding

z^ Encode the states to avoidcritical races z^ Since output needs to be glitch-free, and the output is a functionof the latch outputs, all transitionsmust be race-free† z^ Encode the states such that twoadjacent states are HammingDistance 1 apart z^ If Distance-1 code not possible,one can insert dummy states tomake it possible

C^

F D

010 G

110^101100^110^111110^100

010 Partial State Diagram^ and a Distance-1 Encoding

†^ NOTE:^

Since complete race-free design is expensive, you may design to avoid only critical races

LRS 010 110

Some Observations

z^ Mealy machine (transition assigned output) issimpler than Moore machine for this design^ „^ Mealy could be designed with 2 latches^ ‹

Output Logic will require a 5-variable K-map „ Moore may require 3 or more latches ‹ Next State Logic will require a 6-variable K-map