ECE385
DIGITAL SYSTEMS LABORATORY
© Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Experiment 5
Asynchronous Machine
Design
2
Today’s Topics
zRevisit Experiment 4 (due this week)
Shift Register Memory
RAM with error detection
zExperiment 5 (due next week)
zAsynchronous Machine Design
zCritical Race and State Encoding
zExperiment 5 state table
3
A shift-register memory
New Data In
2-to-1
MUX N-bit SHIFT REGISTER
Data Out
Control
Logic
ADRS
Read/Write
SBR
select
LOAD
W-bit wide
W
SAR Storage
Buffer
Register
4
Experiment 5
zAsynchronous Robot Platform Controller
Three control inputs and six outputs
Design using only gates and latches
No flip-flops or clocks permitted in design
You can assume that only one input changes at
one time and the second change will not occur until
the circuit outputs are stabilized
Outputs must be glitch-free
TASKS
Develop a symbolic State Table
Assign Binary Encoding to States to prevent Races
Develop Latch-input equations from the table
5
Fundamental Mode Asynch Ckts
zFundamental Mode Sequential Circuit
Only one input is allowed to change at one time
zStable State for an input combination
It is the state for which the next state is itself for the
given input combination.
zRaces in Asynchronous Circuits
When the next state of a state has an encoding that
has more than one latch output changing, it is called
a Race.
For example, for Present State <0110> and the
Next State <0000>, the transition may go through
intermediate states <0100>, or <0010>. If the
intermediate states lead to an unintended next state,
then we call it a Critical Race.6
Robot Platform Controller
D1 Q1
D2 Q2
D3 Q3
Latches
Next-State Logic Output Logic
LEFT
RIGHT
SPIN
Q1
Q2
Q3
Go Straight
Turn Left
Turn Right
Spin 180
Halt
Stop/Error
Q1
Q2
Q3
(L,R,S) for Mealy Machine
L
R
S
Moore Machine
