Download AVR DATASHEET | AVR and more Study notes Microcontrollers in PDF only on Docsity!
Features
- High-performance, Low-power Atmel ® AVR ®^ 8-bit Microcontroller
- Advanced RISC Architecture - 131 Powerful Instructions – Most Single-clock Cycle Execution - 32 × 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16MHz - On-chip 2-cycle Multiplier
- High Endurance Non-volatile Memory segments - 32Kbytes of In-System Self-programmable Flash program memory - 1024Bytes EEPROM - 2Kbytes Internal SRAM - Write/Erase Cycles: 10,000 Flash/100,000 EEPROM - Data retention: 20 years at 85°C/100 years at 25°C (1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Programming Lock for Software Security
- JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
- Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x - Byte-oriented Two-wire Serial Interface - Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator
- Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
- I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
- Operating Voltages - 2.7V - 5.5V for ATmega32L - 4.5V - 5.5V for ATmega
- Speed Grades - 0 - 8MHz for ATmega32L - 0 - 16MHz for ATmega
- Power Consumption at 1MHz, 3V, 25 ° C - Active: 1.1mA - Idle Mode: 0.35mA - Power-down Mode: < 1μA
8-bit
Microcontroller
with 32KBytes
In-System
Programmable
Flash
ATmega
ATmega32L
Pin
Configurations
Figure 1. Pinout ATmega
(XCK/T0) PB (T1) PB (INT2/AIN0) PB (OC0/AIN1) PB (SS) PB (MOSI) PB (MISO) PB (SCK) PB RESET VCC GND XTAL XTAL (RXD) PD (TXD) PD (INT0) PD (INT1) PD (OC1B) PD (OC1A) PD (ICP1) PD
PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)
PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO)
(MOSI) PB (MISO) PB (SCK) PB RESET VCC GND XTAL XTAL (RXD) PD (TXD) PD (INT0) PD
(INT1) PD3(OC1B) PD4(OC1A) PD5(ICP1) PD6(OC2) PD
VCCGND
(SCL) PC0(SDA) PC1(TCK) PC2(TMS) PC
PB4 (SS)PB3 (AIN1/OC0)PB2 (AIN0/INT2)PB1 (T1)PB0 (XCK/T0)GNDVCCPA0 (ADC0)PA1 (ADC1)PA2 (ADC2)PA3 (ADC3)
PDIP
TQFP/MLF
Note: Bottom pad should be soldered to ground.
The Atmel®^ AVR ®^ AVR core combines a rich instruction set with 32 general purpose working reg- isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega32 provides the following features: 32Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary- scan, On-chip Debugging support and programming, three flexible Timer/Counters with com- pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil- lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Inter- rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso- nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The Atmel AVR ATmega32 is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits.
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have sym- metrical drive characteristics with both high sink and source capability. When pins PA0 to PA are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32 as listed on page
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. The TD0 pin is tri-stated unless TAP states that shift out data are entered. Port C also serves the functions of the JTAG interface and other special features of the ATmega32 as listed on page 60.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega32 as listed on page
RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
- Shorter pulses are not guaranteed to generate a reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con- nected to V (^) CC , even if the ADC is not used. If the ADC is used, it should be connected to V (^) CC through a low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.
About Code
Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documen- tation for more details.
AVR CPU Core
Introduction This section discusses the Atmel ®^ AVR ®^ core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
Architectural
Overview
Figure 3. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16- or 32-bit instruction.
Flash Program Memory
Instruction Register
Instruction Decoder
Program Counter
Control Lines
32 x 8 General Purpose Registrers
ALU
Status and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data SRAM
Direct AddressingIndirect Addressing
Interrupt Unit SPI Unit Watchdog Timer
Analog Comparator
I/O Module 2
I/O Module
I/O Module n
Status Register The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as:
- Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. - Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. - Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. - Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. - Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. - Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. - Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
- Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the Atmel ®^ AVR ®^ Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are sup- ported by the Register File:
- One 8-bit output operand and one 8-bit result input
- Two 8-bit output operands and one 8-bit result input
- Two 8-bit output operands and one 16-bit result input
- One 16-bit output operand and one 16-bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.
7 0 Addr. R0 $ R1 $ R2 $ … R13 $0D General R14 $0E Purpose R15 $0F Working R16 $ Registers R17 $ … R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte
Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk (^) CPU , directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destina- tion register.
Figure 7. Single Cycle ALU Operation
Reset and
Interrupt Handling
The Atmel ®^ AVR ®^ provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Pro- gram Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Pro- gramming” on page 256 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
clk
1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
T1 T2 T3 T
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T
clk (^) CPU
- The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash section by pro- gramming the BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self- Programming” on page 244.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */
ATmega
Memories
This section describes the different memories in the Atmel®^ AVR ®^ ATmega32. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega32 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
In-System
Reprogrammable
Flash Program
Memory
The ATmega32 contains 32 Kbytes On-chip In-System Reprogrammable Flash memory for pro- gram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K ×
- For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32 Pro- gram Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page
- “Memory Programming” on page 256 contains a detailed description on Flash Program- ming in SPI, JTAG, or Parallell Programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM
- Load Program Memory Instruction Description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim- ing” on page 13.
Figure 8. Program Memory Map
$
$3FFF
Application Flash Section
Boot Flash Section
SRAM Data
Memory
Figure 9 shows how the Atmel®^ AVR ®ATmega32 SRAM Memory is organized. The lower 2144 Data Memory locations address the Register File, the I/O Memory, and the inter- nal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displace- ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data SRAM in the ATmega32 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11.
Figure 9. Data Memory Map Register File R R R
R R R I/O Registers $ $ $
...
$3D $3E $3F
...
$ $ $
$001D $001E $001F
$ $ $
...
$005D $005E $005F
...
Data Address Space
$ $
$085E $085F
...
Internal SRAM
The EEPROM Address Register – EEARH and EEARL
- Bits 15..10 – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. - Bits 9..0 – EEAR9..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
- The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
The EEPROM Data Register – EEDR
- Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
The EEPROM Control Register – EECR
- Bits 7..4 – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. - Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared. - Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
Bit 15 14 13 12 11 10 9 8
- – – – – – EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 X X X X X X X X X
Bit 7 6 5 4 3 2 1 0 MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- – – – EERIE EEMWE EEWE EERE EECR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0
- Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth- erwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
- Wait until EEWE becomes zero.
- Wait until SPMEN in SPMCR becomes zero.
- Write new EEPROM address to EEAR (optional).
- Write new EEPROM data to EEDR (optional).
- Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
- Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 244 for details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM Access, the EEAR or EEDR reGister will be modified, causing the interrupted EEPROM Access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.
- Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor- rect address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical pro- gramming time for EEPROM access from the CPU.
Note: 1. Uses 1MHz clock, independent of CKSEL Fuse setting.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples
Table 1. EEPROM Programming Time
Symbol
Number of Calibrated RC Oscillator Cycles (1)^ Typ Programming Time EEPROM write (from CPU) 8448 8.5ms
