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4 problems, 4 pages Exam Three Solutions 8 April 2009
Problem 1 (3 parts, 30 points) Memory Systems
Part A (12 points) Consider a DRAM chip organized as 4 million addresses of 64-bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two).
number of columns 4M x 64 = 2 22 x 2^6 = 2^28 ; 2^14 = 16K number of words per column (^214) /2^6 = 2^8 = 256 column decoder required ( n to m ) (^) 14 to 16K
total number of bits in address (^) log 2 (4M) = 22 type of mux required ( n to m ) (^) 256 to 1
number of address lines in column offset 8
Part B (10 points) Consider a memory system with 16 million addresses of 32-bit words using a 2 million address by 8-bit word memory DRAM chip.
word address lines for memory system log 2 (16M) = 24 chips needed in one bank (^) 32/8 = 4
banks for memory system 16M / 2M = 8 memory decoder required ( n to m ) (^) 3 to 8
DRAM chips required 4 x 8 = 32
Part C (8 points) Design a 32 million address by 8 bit memory system with four 16M x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if necessary.
D D D D
ADDR
CS D D D D
ADDR
CS D D D D
ADDR
CS
ADDR
25
MSEL
D D D D
16M x 4
D D D D
ADDR
CS
16M x 4
16M x 4
16M x 4
D D D D
A23:A0 24
In
Out
En
1 to 2
Out
A
24
24
24
24
4 problems, 4 pages Exam Three Solutions 8 April 2009
Problem 2 (3 parts, 24 points) Datapath Elements
Part A (6 points) Suppose the following inputs (in hexadecimal) are applied to the 32-bit barrel shifter used in the datapath. Determine the output (in hexadecimal). Assume the shift amount is drawn from the 16-bit immediate value.
Shift Type Shift Amount Input Value Output Value logical 0xFFF4^ EB25ACE7^ 5ACE
arithmetic 0x0008^ CAB15317^ FFCAB
rotate 0x000C^ DE2F1B36^ B36DE2F
Part B (8 points) For each bitwise logical function specification below, determine the LF code (in hexadecimal) to correctly program the logical unit.
X Y Out logical function LF
0 0 LF 0 Y 3
1 0 LF (^1) Y โ
X 4
0 1 LF (^2) X + Y B
1 1 LF 3 X โ
Y 8
Part C (10 points) Given the following finite state diagram, fill in the state table below. The current state variable is S and can be one of two states (0 or 1) and the next state variable is NS.
A/ B/N
B/M
A/
S A / B NS M N
Give the Boolean expression for computing NS in terms of the current state and the input.
NS = S โ A or S โ
B + S โ
A
4 problems, 4 pages Exam Three Solutions 8 April 2009
Problem 4 (2 parts, 20 points) Counters
Part A (10 points) Design a toggle cell using two transparent latches, two 2 to 1 muxes, and one inverter. Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR , clock inputs ฮฆ 1 and ฮฆ 2 , and an output Out. The CLR signal has precedence over TE. Label all signals. Also complete the behavior table for the toggle cell.
In Out
En
Latch
In Out
En
Latch
TE
Out
CLR
In Out S In
In Out S In
TE (^) CLR CLK Out
0 1 โโ Q 0
1 1 โโ Q 0
Part B (10 points) Now combine these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, XOR & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design must support multi-digit systems.
O 0
O 1
O 2
Ext Clr
Ext CE TE Out Clr
TE Out Clr
TE Out Clr
