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chapter 5 morris mano notes, chapter summary.
Typology: Lecture notes
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A set of instructions that specify the operations , operands , and the sequence by which processing has to occur.
A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation) --> macro-operation
Opcode (^) Address Instruction Format
Binary Operand
Instructions(program)
Operands(data)
Processor register (Accumulator, AC)
Memory 15 12 11 0 4096x
15 0
Instruction codes
List of BC Registers DR 16 Data Register Holds memory operand AR 12 Address Register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction Register Holds instruction code PC 12 Program Counter Holds address of instruction TR 16 Temporary Register Holds temporary data INPR 8 Input Register Holds input character OUTR 8 Output Register Holds output character
Registers
Registers in the Basic Computer
11 0 PC
15 0 IR 15 0 TR 7 0 OUTR
15 0 DR 15 0 AC
11 0 AR
INPR
0 7
Memory 4096 x 16
Registers
S2S S0 Bus Memory unit 4096 x 16
LD INR CLR
Address Write Read AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
AC
Adder and logic
E
INPR IR LD
LD INR CLR
TR
OUTR LD
Clock 16-bit common bus
7 1 2 3 4 5 6
Hex Code Symbol I = 0 I = 1 Description AND 0xxx 8xxx AND memory word to AC ADD 1xxx 9xxx Add memory word to AC LDA 2xxx Axxx Load AC from memory STA 3xxx Bxxx Store content of AC into memory BUN 4xxx Cxxx Branch unconditionally BSA 5xxx Dxxx Branch and save return address ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC CLE 7400 Clear E CMA 7200 Complement AC CME 7100 Complement E CIR 7080 Circulate right AC and E CIL 7040 Circulate left AC and E INC 7020 Increment AC SPA 7010 Skip next instr. if AC is positive SNA 7008 Skip next instr. if AC is negative SZA 7004 Skip next instr. if AC is zero SZE 7002 Skip next instr. if E is zero HLT 7001 Halt computer
INP F800 Input character to AC OUT F400 Output character from AC SKI F200 Skip on input flag SKO F100 Skip on output flag ION F080 Interrupt on IOF F040 Interrupt off
Instructions
Instruction Types
A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable.
Functional Instructions
Instructions
Clock
T0 T1 T2 T3 T4 T
T
T
T
T
T
D
CLR SC
D 3 T 4 : SC ← 0
Timing and control
BC Instruction cycle: [Fetch Decode [Indirect] Execute]*
S S S
Bus
Memoryunit 7 Address Read
AR
LD PC
INR
IR
LD (^) Clock
1
2
5
Common bus
T
T
Instruction Cycle
r = D 7 I’ T 3 => Register Reference Instruction Bi = IR(i) , i=0,1,2,...,
Instruction Cycle
Register Reference Instructions are identified when
r: SC ← 0 CLA rB 11 : AC ← 0 CLE rB 10 : E ← 0 CMA rB 9 : AC ← AC’ CME rB 8 : E ← E’ CIR rB 7 : AC ← shr AC, AC(15) ← E, E ← AC(0) CIL rB 6 : AC ← shl AC, AC(0) ← E, E ← AC(15) INC rB 5 : AC ← AC + 1 SPA rB 4 : if (AC(15) = 0) then (PC ← PC+1) SNA rB 3 : if (AC(15) = 1) then (PC ← PC+1) SZA rB 2 : if (AC = 0) then (PC ← PC+1) SZE rB 1 : if (E = 0) then (PC ← PC+1) HLT rB 0 : S ← 0 (S is a start-stop flip-flop)
AND to AC
D 0 T 4 : DR ← M[AR] Read operand D 0 T 5 : AC ← AC ∧ DR, SC ← 0 AND with AC
ADD to AC
D 1 T 4 : DR ← M[AR] Read operand D 1 T 5 : AC ← AC + DR, E ← Cout, SC ← 0 Add to AC and store carry in E
MR Instructions
Symbol OperationDecoder Symbolic Description AND D 0 AC ← AC ∧ M[AR] ADD D 1 AC ← AC + M[AR], E ← Cout LDA D 2 AC ← M[AR] STA D 3 M[AR] ← AC BUN D 4 PC ← AR BSA D 5 M[AR] ← PC, PC ← AR + 1 ISZ D 6 M[AR] ← M[AR] + 1, if M[AR] + 1 = 0 then PC ← PC+
MR Instructions
ISZ: Increment and Skip-if-Zero
D 6 T 4 : DR ← M[AR] D 6 T 5 : DR ← DR + 1 D 6 T 6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
MR Instructions
Memory-reference instruction
DR <- M[AR] DR <- M[AR] DR <- M[AR] M[AR] <- ACSC <- 0
AND ADD LDA STA
AC <- AC DR SC <- 0
AC <- AC + DR E <- Cout SC <- 0
AC <- DR SC <- 0
D T 0 4 D T 1 4 D T 2 4 D T 3 4
D T 0 5 D T 1 5 D T 2 5
PC <- AR SC <- 0
M[AR] <- PC AR <- AR + 1
DR <- M[AR]
BUN BSA ISZ D T 4 4 D T 5 4 D T 6 4
DR <- DR + 1
D T 5 5 D T 6 5 PC <- AR SC <- 0
M[AR] <- DR If (DR = 0) then (PC <- PC + 1) SC <- 0
D T 6 6
∧
loop: If FGI = 1 goto loop INPR ← new data, FGI ← 1
loop: If FGO = 1 goto loop consume OUTR, FGO ← 1
-- CPU -- -- I/O Device --
/* Input / / Initially FGI = 0 */ loop: If FGI = 0 goto loop AC ← INPR, FGI ← 0
/* Output / / Initially FGO = 1 */ loop: If FGO = 0 goto loop OUTR ← AC, FGO ← 0
I/O and Interrupt
Start Input
FGI ← 0
FGI=
AC ← INPR
More Character
END
Start Output
FGO ← 0
FGO=
More Character
END
OUTR ← AC
AC ← Data yes
no
yes
no
FGI=0 FGO=
yes
no yes no
D 7 IT 3 = p IR(i) = Bi, i = 6, … , 11
INP pB 11 : AC(0-7) ← INPR, FGI ← 0 Input char. to AC
OUT pB 10 : OUTR ← AC(0-7), FGO ← 0 Output char. from AC
SKI pB 9 : if(FGI = 1) then (PC ← PC + 1) Skip on input flag
SKO pB 8 : if(FGO = 1) then (PC ← PC + 1) Skip on output flag
ION pB 7 : IEN ← 1 Interrupt enable on
IOF pB 6 : IEN ← 0 Interrupt enable off
