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Sequential Logic Design: Creating a 3-bit Gray Code Counter - Prof. Charles Stroud, Study notes of Electrical and Electronics Engineering

Auburn University (AU)Electrical and Electronics Engineering
Prof. Charles Stroud

The steps to design a 3-bit gray code counter using sequential logic. The process includes deriving a circuit state diagram, creating a state table, choosing flip-flops, creating a circuit excitation table, generating k-maps, and obtaining minimized sop equations. The document also covers the differences between mealy and moore models in sequential logic.

Typology: Study notes

Pre 2010

Uploaded on 08/18/2009

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koofers-user-2de 🇺🇸

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C. E. Stroud Sequential Logic Design (11/03) 1
Basic Sequential Design Steps
• Derive circuit state diagram from design specs
• Create state table
• Choose flip-flops
• Create circuit excitation table
• Construct K-maps for:
¾flip-flop inputs
¾primary outputs
• Obtain minimized SOP equations
• Draw logic diagram
• Simulate to verify design & debug as needed
• Perform circuit analysis & logic optimization
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Download Sequential Logic Design: Creating a 3-bit Gray Code Counter - Prof. Charles Stroud and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!

C. E. Stroud

Sequential Logic Design (11/03)

Basic Sequential Design Steps

•^

Derive circuit state diagram from design specs

•^

Create state table

•^

Choose flip-flops

•^

Create circuit excitation table

•^

Construct K-maps for:^ ¾

flip-flop inputs

primary outputs

•^

Obtain minimized SOP equations

•^

Draw logic diagram

•^

Simulate to verify design & debug as needed

•^

Perform circuit analysis & logic optimization

C. E. Stroud

Sequential Logic Design (11/03)

Sequential Design Example

Design a 3-bit gray code counter with

active low synchronous reset (R)

1

1

1

1

1 1

1 R=0R=

0 (^00) 0

0

State Diagram^0

XXX

Next state(X Y Z)

Current state

(X Y Z)

Inputs

R

State Table

State order:

X Y Z

0

C. E. Stroud

Sequential Logic Design (11/03)

3-bit Gray Code Counter (cont)

-^

Generate K-Maps & obtain minimized SOPs

X

X

X

X

00 01 11 10^1

RX

YZ

X

X

RX

YZ

X

X

00 01 11 10^1

RX

YZ

X^1

X

X

00 01 11 10X

RX

YZ

RX

YZ

Jx =Jx

= RYZ

RYZ’

Kx = R’ + Y’Z’

Dy =Dy

= RYZ

RYZ’

’ + RX+ RX’

’ZZ

SzSz = RXY + RX

= RXY + RX’

’YY’

Rz = R’ + XY’ + X’Y

Further reductions:Rz =Rz

= R

R’

’ + X+ X

YY

Sz = R(XSz

= R(X

Y)’Y)

= (R’= (R

’ + X+ X

Y)’Y)

= Rz=

Rz’

C. E. Stroud

Sequential Logic Design (11/03)

5

3-bit Gray Code Counter (cont)

• Logic diagram• Next would

come designverification vialogic simulation^ ¾

Debug asnecessary toobtain workingcircuit

Update logicdiagram, logicequations, etc.to reflect fixes

Jx

X X

Kx Clk Sz

Z Z

Dy Rz Clk

Y Y

Clk

R X Y

Y’Z’

YZ’ X’Z

C. E. Stroud

Sequential Logic Design (11/03)

Mealy & Moore State Diagrams

  • Mealy model

¾

Outputs associatedwith state transition ¾

Output valuesshown with inputs

  • Moore model

¾

Outputs associatedwith states only ¾

Output valuesshown with states

Input

/ Output

StateorderXY States/ Output

C. E. Stroud

Sequential Logic Design (11/03)

8

Mealy & Moore State Tables

101110 X

O

Mealy

D^ Y^100001 X

X X X X 1 1 0

O

Moore

D

X

Y

X

Y

X

In

Note: next state (next state logic) is same forboth Mealy & Moore – only output is different

C. E. Stroud

Sequential Logic Design (11/03)

10

Mealy & Moore Design Examples

D

X^

= In’Y + InX’Y’

D

Y^

= InX + In’X’Y’

O

Mealy

= In’Y’ + InX’

O

Moore

= X’Y’

X X

Y X Y

In

Y Y

X X Y

X X

Y X Y

In

Y Y

X X Y X^ Y

OMoore

Y X

OMealy

Note: O

Mealy

is

a function of In but O

Moore

is not

a function of In

Clk

Clk