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Digital Logic: Exam 4 Solutions for COE/EE 243, Exams of Electrical and Electronics Engineering

University of Idaho (U of I)Electrical and Electronics Engineering

The solutions to exam 4 for the digital logic course (coe/ee 243) held in spring 2003. It includes finding transition tables and state tables for a mealy sequential circuit, determining the starting state based on input and output sequences, and realizing a sequential circuit using d flip-flops. The document also includes combinational logic expressions and a logic circuit diagram.

Typology: Exams

Pre 2010

Uploaded on 08/19/2009

koofers-user-svk
koofers-user-svk 🇺🇸

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COE/EE 243
Digital Logic Session 34; Page 1/3
Spring 2003
COE/EE 243 Sample Exam #4 Solution
1. (16 pts) Find the transition table and the state table for the Mealy sequential circuit below.
X2
X1
C’
Clock
C
C
C
Q
Q
Q
Q
Q
Q
D
D
D
a
c
b
Z
A
A’
B
B’
C
DC
Z
X1
X2
A
C
¼
DA
X2
A
DB
X1
B
pf3
pf4

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Digital Logic Spring 2003

COE/EE 243 Sample Exam #4 Solution

  1. (16 pts) Find the transition table and the state table for the Mealy sequential circuit below.

X 2

X (^1)

C’

Clock

C

C

C

Q

Q

Q

Q

Q

Q

D

D

D

a

c

b

Z

A

A’

B

B’

C

DC Z X 1 X 2 A C

D A X 2  A

D B X 1  B

Digital Logic Spring 2003

A  B  C  Z A  B  C 

ABC X 1 X 2 00 01 11 10 00 01 11 10 ABC 00 01 11 10

000 000 100 110 010 0 0 0 0 S 0 S 0 S 4 S 6 S 2

001 000 100 110 010 0 0 0 0 S 1 S 0 S 4 S 6 S 2

010 010 110 100 000 0 0 0 0 S 2 S 2 S 6 S 4 S 0

011 010 110 100 000 0 0 0 0 S 3 S 2 S 6 S 4 S 0

100 100 000 011 110 0 0 1 0 S 4 S 4 S 0 S 3 S 6

101 100 000 010 110 0 0 0 0 S 5 S 4 S 0 S 2 S 6

110 110 010 001 100 0 0 1 0 S 6 S 6 S 2 S 1 S 4

111 110 010 000 100 0 0 0 0 S 7 S 6 S 2 S 0 S 4

  1. (8 pts) The sequential circuit below yields an output sequence of Z 11011111 when you apply the input sequence X 01101010. What is the starting state A?

Z

C

A (^) Q

A’ (^) Q K

J

Clock

X

Since X 0 initially and Z 1, the A  X Z 1 requires that A=1 initially.

  1. (16 pts) Determine the D flip-flop realization of the sequential circuit specified by the following transition table. Write the combinational logic expressions for the flip-flip inputs and draw the logic circuit diagram.

A+B+C+ Z

ABC X=0 X=1 X=0 X=

111 - - -^ - - -^ -^ -

Digital Logic Spring 2003

  1. (10 pts) The circuit below has three D flip-flops, one is level triggered (i.e. triggers based on the level of the clock). The other two are edge triggered, one on the positive-edge and the other on the negative-edge. Complete the timing diagram by filling in the waveforms for A , B , and C.

X

A

C

B

Clock

Propagation delay is assumed to be 1/2 division

C

A B C

D Q

Q

D Q

C Q

D Q

C Q

X

Clock