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Biasing methods to Achieve a
Stable Q-Point
Purpose:
Equipment
Pre-lab Preparation
Discussion: Base Bias
The saturation region
The cutoff region
The active region
- To examine different types of bias used to set up a stable operating point.
- To sketch and label a DC load line for a transistor bias.
1- DMM
1- dc ammeter 1- dc voltmeter 1- dc Power Supply Meter and Test Leads 3- Transistors - 2N3904 NPN (Q , Q , Q ) Resistors ( 330 , 1 k , 2 k , 10 k , 680 k )
- Perform the dc analysis & complete the calculated portion of Tables 1 & 2.
- Find I & V and plot the load line and plot the calculated Q point for both circuits.
The transistor has three regions of operation and.
is when the transistor is in its totally “on” state. It is acting like a closed switch, and the collector current is at its maximum.
is when the transistor is in its totally “off” state. It is acting like an open switch and the collector current is at its minimum. (It should be very close to zero).
is when the transistor is anywhere between saturation and cutoff. When it is in this region, the collector current is controlled by the base current. Remember that our transistor is basically a simple device. Look at Figure 1 to the right. It is an example of a circuit. If we have a small amount of current flowing in the base circuit, we should have a larger current flowing in the collector circuit when the transistor is in the active region. The ratio between these two currents is called the dc current gain of the transistor (h ). In Fig. 1 the base current is 19.78 A. This base current is determined by the value of R. The collector current is 2.97 mA. This is determined by the dc current gain of this transistor. Since this transistor has a current gain of 150, the collector current I , is 150 times larger than the base current. If this transistor had a gain of less than 150, then I would also be less. Conversely, if this transistor had a gain of more than 150, then I would be higher. As you can see, for a base bias circuit, I can be different for each transistor. The 2N3904 used here can have a current gain of
anywhere from 100 to 300. This means that I can vary widely depending on the transistor we use. because it can vary widely with different transistors of the same type.
Show all Calculations
saturation, active, cutoff
Base Bias
I is considered to be unstable
1 2 3
C(sat) CE(off)
FE B
C C C C C
W W W W W
m
C
V (^) CC= 10V
E
B
C
R 1 k
C W
h (^) FE=
470 k W
Figure 1
0.7 V
0 V
7 V
I (^) B = 19.78 m A
I (^) C = 2.97 mA
R (^) b 10 V
Example of Base Bias
Biasing methods
The Q Point and Midpoint Bias
The Q point refers to the collector current. In the circuit shown in Fig. 1, the collector current is 2.97 mA. This is referred to as the Q point because the collector current will remain at 2.97 mA provided that no other voltages affect the circuit. In other words this means that a current of 2.97 mA will normally flow in the collector circuit with no signal applied. Our purpose here is to eventually use our transistor circuit as an amplifier. We need to have the Q point as close to the centre of the load line is possible. In the case in Fig. 1, the maximum collector current that can flow is 10 mA.( I )This
means the ideal Q point is at 5 mA. When the Q point is at 5 mA, the value of V ( the voltage from collector to emitter) will be ½ of
V or 5 V. Note that this is also at the midpoint.
Look at Fig. 1. Is this particular circuit midpoint biased? Your answer should be. We have already determined that midpoint bias for this circuit is when the collector current is 5 mA and V is 5 V (½ V ). The Q point for this circuit is of the
load line at I =2.97 mA and V = 7 V. See the load line shown below.
It is important that our initial Q point be in the centre of the load line. If it is located higher up the load line, or lower down the load line, our signal output from the transistor will likely be distorted. The problem is that h varies from transistor to transistor. Because of this, our Remember that our purpose is to consistently produce a Q point that is near the centre of the load line. The base bias circuit just doesn’t do it. The reason is that the Q point is dependent on the value of h. We will attempt to prove this point with the circuit shown in Figure 2.
Calculate base current, collector current , Icq
and V for the circuit shown in Figure 2. Insert your answers on the line in Table 1.
C(sat)
CE CC
CE CC C CE
FE
FE
CEQ
no
below the centre
Q point is unpredictable if we use the circuit shown in Fig. 1.
Calculated Values
A Stable Q Point – Why do we need it?
base bias
Base Bias
Dc analysis Worksheet (Pre Lab)
Show all Calculations
V (^) CC= 10V
E
B
C
R 1 k
C W
h (^) FE=
470 k W
Figure 1
0.7 V
0 V
7 V
I (^) B = 19.78 m A
I (^) C = 2.97 mA
R (^) b 10 V
Example of Base Bias
(^00 1 2 3 4 5 6 7 8 9 10 )
1
2
3
4
5
6
7
8
9
10
11
12
mA
I (^) C
V (^) CE DC Load Line for Figure 1
Actual Q Point
Desired Q Point
V (^) CC= 20V
E
B
C
R
2 k
C W
h (^) FE=
680 k W
Figure 2
R (^) b
I B
I C
Voltage Divider Bias
Discussion
Dc analysis worksheet (Pre-Lab)
Voltage divider biased provides us with a much more Stable Q- point. With this type of bias, the h of the transistor plays no part in determining the Q point. In this circuit, it is the .
This means that we can expect the Q-point to fall on the load line in the same place when we change the transistor to another of the same type. The following exercise will show this.
Calculate V ,
V , I , and V for the circuit shown in Figure 4.
Insert your answers on the line in Table 2.
FE
B E CQ CEQ
emitter resistor R that determines the collector current
Calculated Values
E
Show all Calculations
Biasing methods
330 W
2 k W
10 k W 1 k W
V (^) CC 15 V
R (^2) R (^) E
R 1 R (^) C
2N 3904 2N
E B C
Figure 4
Voltage Divider Bias
h (^) FE 173
I (^) C
Calculated Values
Table 2 VDB Bias I^ CQ
Measured Values for Q 1
Measured Values for Q 2
Measured Values for Q 3
V B V E V CEQ
Plot the load line for the Voltage Divider Bias Circuit shown in Figure 4 (Pre-Lab)
Find I
Find V
- Find both ends of the load line, plot these values, then draw a straight line to join the points.
I is the maximum current that can flow when the transistor
is saturated. This means that the transistor is acting like a closed switch as shown to the right. At this end of the load line, I is at its maximum and V is at zero. The current flowing in the circuit
is determined by the total resistance in the circuit. Notice that this time, there are two resistors in the circuit. The total resistance is the addition of these.
I ____________
V is the voltage that appears across the transistor from collector to emitter when the transistor in acting like
an open switch. V is V when the transistor is in this region. The collector current is zero when the transistor is in cutoff.
V ___________
C(sat)
CE(off)
C(sat)
C CE
C(sat)
CE(off) CE(off) CC
CE(off)
Plot the load line on graph below Plot your calculated Q point on the graph and label it.
Dc analysis worksheet ( Pre-Lab continued )
Finding the ends of the Load Line for VDB Figure 5
V (^) CC= 15V
E
C
R 1 k
C W
Collector to emitter acts like a short circuit
VCE(off) (^) = VCC
V (^) CC= 15V
E
C Collector to emitter acts like an open circuit
R 1 k
C W
R 330
E W
R 330
E W
I (^) C(sat) =^ R (^) C
VCC +R (^) E
Procedure: Voltage Divider Bias Do this part in the Lab
Build the circuit shown in Figure 4 on your breadboard.
Measure the value of V , V I , and V.
Record these values in Table 2 in the row for Q.
Repeat the above for Q and Q.
Plot the measured Q points for all three transistors on the load line you created above.
Label the Q points Q , Q , Q.
B E, CQ CEQ 1
2 3
1 2 3
(The Q points should plot almost on top of each other.)
0 0 1 2 3 4 5 6 7 8 9 10 11 12
1
2
3
4
5
6
7
8
9
10
11
12
mA
I C
13 14 15 16 VCE
Load Line for Voltage Divider Bias (Figure 4)
