Binary Numbers - Advanced Digital Design - Homework, Exercises of Verilog and VHDL

These homework exercises are quite informative in Advanced Digital Design. The main points in these slides are:Binary Numbers, Leftmost Position, Complement Form, Arithmetic Operations, Sequential Circuit, Least Common Multiple, Unsigned Numbers, Full Adders, D Flip-Flops, Boolean Gates, Combinational Circuit, Sequential Multiplier

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Northwestern University Oct 25, 2011
Electrical Engineering and Computer Science Handout #8
EECS303: Advanced Digital Design, Fall 11 Due: Nov 1
Prof. Hai Zhou
Homework 3
You may discuss the assignments with your classmates but need to write down your solutions
independently. Be careful with your handwriting. Unclear solutions will be assumed wrong.
1. (10 pts) The following binary numbers have a sign in the leftmost position and, if
negative, are in 2s complement form. Perform the indicated arithmetic operations
(show your work) and verify the answers.
(a) 100111 + 111001
(b) 001011 + 100110
(c) 110001 โˆ’010010
(d) 101110 โˆ’110111
2. (25 pts) Design a LCM machine which is a sequential circuit that compute the Least
Common Multiple of two 4-bit unsigned numbers aand b, using the following algo-
rithm:
x, y, u, v := a, b, a, b
do
x>yโ†’x, u := xโˆ’y, u +v
y > x โ†’y, v := yโˆ’x, v +u
od
output ((u+v)/2);
The available basic elements include full adders, D flip-flops, and multiplexers, in
addition to Boolean gates. Assume that each basic element takes 1 unit of time, what
is the minimum clock period you can use.
3. (15 pts) Design a combinational circuit that compares two 4-bit unsigned numbers A
and Bto see whether Bis greater than A. The circuit has one output X, such that
X= 1 if and only if A < B.
4. (25 pts) Design a sequential multiplier that multiplies two 4-bit unsigned numbers
Aand B. The available basic elements include one 4-bit adder, D flip-flops, and
multiplexers, in addition to Boolean gates. Assume that each basic element takes 1
unit of time, what is the minimum clock period you can use.
5. (25 pts) Implement to the gate and full adder level an ALU bit slice with three
operation selection inputs S2, S1, S0, that implements the following eight functions of
pf2

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Northwestern University Oct 25, 2011 Electrical Engineering and Computer Science Handout # EECS303: Advanced Digital Design, Fall 11 Due: Nov 1 Prof. Hai Zhou

Homework 3

You may discuss the assignments with your classmates but need to write down your solutions independently. Be careful with your handwriting. Unclear solutions will be assumed wrong.

  1. (10 pts) The following binary numbers have a sign in the leftmost position and, if negative, are in 2s complement form. Perform the indicated arithmetic operations (show your work) and verify the answers.

(a) 100111 + 111001 (b) 001011 + 100110 (c) 110001 โˆ’ 010010 (d) 101110 โˆ’ 110111

  1. (25 pts) Design a LCM machine which is a sequential circuit that compute the Least Common Multiple of two 4-bit unsigned numbers a and b, using the following algo- rithm:

x, y, u, v := a, b, a, b do x > y โ†’ x, u := x โˆ’ y, u + v y > x โ†’ y, v := y โˆ’ x, v + u od output ((u + v)/ 2 );

The available basic elements include full adders, D flip-flops, and multiplexers, in addition to Boolean gates. Assume that each basic element takes 1 unit of time, what is the minimum clock period you can use.

  1. (15 pts) Design a combinational circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than A. The circuit has one output X, such that X = 1 if and only if A < B.
  2. (25 pts) Design a sequential multiplier that multiplies two 4-bit unsigned numbers A and B. The available basic elements include one 4-bit adder, D flip-flops, and multiplexers, in addition to Boolean gates. Assume that each basic element takes 1 unit of time, what is the minimum clock period you can use.
  3. (25 pts) Implement to the gate and full adder level an ALU bit slice with three operation selection inputs S 2 , S 1 , S 0 , that implements the following eight functions of

the two data inputs A and B (and carry-in Ci): S 2 S 1 S 0 ALU operation 0 0 0 Fi = 0 0 0 1 Fi = B โˆ’ A 0 1 0 Fi = A โˆ’ B 0 1 1 Fi = A + B 1 0 0 Fi = AxorB 1 0 1 Fi = AorB 1 1 0 Fi = AandB 1 1 1 FI = 1