Sequential Machine Modeling - HDL Design - Lecture Slides, Slides of Verilog and VHDL

Download Sequential Machine Modeling - HDL Design - Lecture Slides and more Slides Verilog and VHDL in PDF only on Docsity!

Project Step 9

Beyond the ALU and Datapath.

Sequential Machine Modeling

exercise.

The sequential machine modeling style

• In the lecture on state machine modeling

introduces how three processes can be used to

model the state machine.

• This style is good for documentation,

simulation, and synthesis.

• And it also maps across multiple HDLs.

More on the controller

• Modeling to the

SAR Controller and

SAR Control

Register

• This is the heart of a

successive

approximation A-

to-D unit

SAR

SAR Controller/Reg.

D to A converter

analoginput 8

over_under start sarclk eoc sar_val (^8) digital_val

Analog units

• D-to-A converter is an

analog circuit

• Analog comparator for

comparison of the current

converter value to the

input – provides a single

bit digital output.

• These analog units are

modeled in the testbench

algorithmically

SAR

SAR Controller/Reg.

D to A converter

inputanalog^8

over_under start sarclk eoc sar_val (^8) digital_val

The digital portion -

• Outputs
  • eoc indicator signal line – indicates the end of the conversion and that the value on the digital_val output is valid
  • digital_val – the 8-bit digital conversion value
  • sar_val – an 8-bit output that is sent to the D-to-A converter – signal is internal to the entire unit mixed signal unit
• Note that part of the entire unit is modeled by the

testbench. The assignment is modeling of the

controller only, i.e., the digital portion.

Conversion basics

• The input range is 0-5Volts

• Starting state for converter state machine

(1st^ approximation) is 1000 0000 or 2.5V

• If this is less than input the next bit is set to 1,

1100 0000 and again a comparison is made.

• If this is greater than the input the 1 st^ bit is set

0 before the next bit position is set to 1, giving

State machine

• State machine has multiple states

• Ready to convert
• S1, S2, S3, S4, S5, S6, S7 while converting
• EOC – done converting

Notes on operation

• Notes on operation
  • Start will transition high when the analog input is valid and remains high during the conversion
  • EOC is asserted and system asserting start will de-assert it
  • Once start returns low, EOC is to be reset.
• DO NOT SIMULATE UNTIL time’high
  • TESTBENCH NEVER GOES QUIESENT
  • Testbench has a free running clock, sarclk
  • run 20 us instead
  • USE THE .DO files – It set up the waveform. This is needed as it present the data appropriately.