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Binary Representation - Organization and Logical Design - Exam, Exams of Organization Theory and Design

Main points of this exam paper are: Octal Representation, Hexadecimal, Binary Representation, Simplified Expression, Karnaugh Map, Possible Expression, Circuit, Directly Implements, Logic Function, Circuit

Typology: Exams

2012/2013

Uploaded on 03/27/2013

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kalii 🇮🇳

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CS/EE 260 – Exam 1
Spring 2000
No books, no notes, no calculators. Write in the spaces provided. Be neat.
1. (5 points) What is the binary representation of 678? What is the octal representation?
Hexadecimal?
2. (5 points) Use a Karnaugh map to find the simplest possible expression for
F(A,B,C,D)=Σm(0,1,2,5,6,7), d(A,B,C,D)=Σm(8,10,12,13,15).
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CS/EE 260 – Exam 1

Spring 2000

No books, no notes, no calculators. Write in the spaces provided. Be neat.

  1. (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal?
  2. (5 points) Use a Karnaugh map to find the simplest possible expression for F ( A,B,C,D )=Σ m (0,1,2,5,6,7), d ( A,B,C,D )=Σ m (8,10,12,13,15).
  1. (5 points) Draw a schematic for a circuit that directly implements the logic function A + B ′ C +( A ( B + C ′)).

Simplify the logic expression and draw a schematic for the circuit that implements the simplified expression.

  1. (5 points)Consider the Karnaugh map shown below. How many terms are there in the simplest sum-of-products expression for this Karnaugh map? Is there any four input logic function that requires more terms? Why or why not?

0

AB

1 0

1 0 1 0

1

CD

0 1 0

1

0 1 0

1

  1. (15 points) In the circuit shown below output di is the odd function computed over inputs

a 0 , a 1 ,... , ai. If each exclusive-or gate has a propagation delay of 1 ns, what is the worst-case delay in this circuit (the time from when some input changes to latest time that some output changes)? Show a logically equivalent circuit using only 2 input exclusive-or gates that has a worst-case delay of 3 ns.

a 0 a 1 a 2

d 1

a 3

d 2

a 4

d 3

a 5

d 4

a 6

d 5

a 7

d 6

. d

7

  1. (10 points) Write a VHDL specification for a circuit with inputs A , B , C , D and outputs X = ABC ′ + A ( C + B ′ D ′) and Y = ( B + C ′)( A ′+ D ).
  2. (5 points) Consider the sequential circuit shown below. Fill in the waveform for output Z in the timing diagram.

D

>C

Q B

A. Z

C B

A

C

Z