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CS/EE 260 – Exam 1
Spring 2000
No books, no notes, no calculators. Write in the spaces provided. Be neat.
- (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal?
678 = 512 + 166 29 166 = 128 + 38 27 38 = 32 + 6 25 6 = 4 + 2 22 2 = 2 + 0 21
So, 678 = 1010100110 2 = 1246 8 = 2a6 16.
- (5 points) Use a Karnaugh map to find the simplest possible expression for F ( A,B,C,D )=Σ m (0,1,2,5,6,7), d ( A,B,C,D )=Σ m (8,10,12,13,15).
F = A ′ B ′ C ′ + A ′ CD ′ + BD
1
AB
0 1
1 0
1 1
1
00 01
CD
11 10
x
x 0
x
00
01
11
10
x
0 x
0
- (5 points) Draw a schematic for a circuit that directly implements the logic function A + B ′ C +( A ( B + C ′)).
Simplify the logic expression and draw a schematic for the circuit that implements the simplified expression.
A + B ′ C +( A ( B + C ′)) = A (1 +B + C ′)+ B ′ C = A + B ′ C
- (5 points)Consider the Karnaugh map shown below. How many terms are there in the simplest sum-of-products expression for this Karnaugh map? Is there any four input logic function that requires more terms? Why or why not?
There are eight terms in the simplest sum of products expression, since none of the eight minterms can be combined with other minterms.
There is no four input logic function that requires more terms. Any logic function with fewer than eight minterms obviously requires fewer terms in the simplest sum of products expression. In any logic function with more than eight minterms, you can combine some minterms into common terms, resulting in no more than eight altogether.
0
AB
1 0
1 0 1 0
1
CD
0 1 0
1
0 1 0
1
B
C
A
C
B
A
- (15 points) In the circuit shown below output di is the odd function computed over inputs
a 0 , a 1 ,... , ai. If each exclusive-or gate has a propagation delay of 1 ns, what is the worst-case delay in this circuit (the time from when some input changes to latest time that some output changes)? Show a logically equivalent circuit using only exclusive-or gates that has a worst- case delay of 3 ns.
The worst-case delay for this circuit is 7 ns. Changes in a 0 and a 1 can affect d 7 after 7 ns, but changes to other inputs will cause changes to outputs after less than 7 ns.
a 0 a 1 a 2
d 1
a 3
d 2
a 4
d 3
a 5
d 4
a 6
d 5
a 7
d 6
. d
7
a 0 a 1
d 1
. d^2
d 3
d 4
d 5
d 6
d 7
a 2 a 3
a 4 a 5
a 6 a 7
- (10 points) Write a VHDL specification for a circuit with inputs A , B , C , D and outputs X = ABC ′ + A ( C + B ′ D ′) and Y = ( B + C ′)( A ′+ D ).
library IEEE; use IEEE.std_logic_1164.all; entity foo is port(A,B,C,D: in std_logic; X,Y: out std_logic); end foo;
architecture dataflow of foo is begin X <= (A and B and (not C)) or (A and (C or ((not B) and (not D)))); Y <= (B or (not C)) and ((not A or D); end dataflow;
- (5 points) Consider the sequential circuit shown below. Fill in the waveform for output Z in the timing diagram. Assume Z =0 initially.
D
>C
Q B
A. Z
C B
A
C
Z
D
>C
Q B
Equivalent circuit
. Z
C B
A
C
Z
A
