Branch Prediction: Techniques and Strategies for Reducing Branch Costs - Prof. Alaa R. Ala, Study notes of Computer Architecture and Organization

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© Copyright by Alaa Alameldeen and Haitham Akkary 2008

Branch Prediction

Portland State University ECE 587/

Branch Penalty

n Example: Comparing perfect branch prediction to 90%, 95%, 99% prediction accuracy, and to no branch prediction u Processor has a 20-stage 6-wide pipeline, incorrectly predicted branch leads to pipeline flush u Program can have an average of 4 instructions retire per cycle, has 100,000 conditional branches out of 1 million instructions u Perfect BP: IPC = 1,000,000/250,000 = 4. u 90% BP accuracy: 1/10 branches incorrectly predicted Ø IPC = 1,000,000/(250,000 + 0.1x100,000x20) = 2.22 (80% slower) u 95% BP accuracy: 1/20 branches incorrectly predicted Ø IPC = 1,000,000/(250,000 + 0.05x100,000x20) = 2.85 (40% slower) u 99% BP accuracy: 1/100 branches incorrectly predicted Ø IPC = 1,000,000/(250,000 + 0.01x100,000x20) = 3.70 (8% slower) u No BP: Fetch stalled until branch is resolved (5 pipeline stages) Ø IPC = 1,000,000/(250,000 + 100,000x5) = 1.33 (300% slower – 3x)

Predicting Conditional Branch Outcomes

n Simplest dynamic branch prediction scheme uses a branch-prediction buffer or branch history table u Small memory indexed by the lower portion of the branch address u Stores previous branch outcomes to predict next outcome u Memory is not tagged u Prediction may have been put in the entry by a different branch

PC

1K entries prediction buffer

PC [11:2]

Predicting Conditional Branch Outcomes

n 1-bit prediction buffer stores the last executed branch outcome, and uses it to predict the next outcome u If bit = 1, branch is predicted taken u If bit = 0, branch is predicted not-taken

n A simple 1-bit scheme has a performance shortcoming u A series of branch outcomes and corresponding predictions : outcomes 1111011110111101 predictions 111101111011110 mispredictions 111 10 111 10 111 10

2-bit Saturating Counter State

Machine

Predict taken “11”

Predict taken “10”

Predict not taken “01”

Predict not taken “00”

T

T NT

NT

T

NT

T

NT

Predicting Conditional Branch Outcomes

n Assuming initial state to be “11”, branch outcomes and corresponding predictions now look as follows:

outcomes 1111011110111101 states 333323333233332 predictions 111111111111111 mispredictions 111 1 1111 1 1111 1 1

Two-Level Adaptive Branch

Prediction

n Two main structures u Branch History Register (BHR) or Branch History Table (BHT) u Pattern History Table (PHT) u Basic structure of the branch predictor: Yeh&Patt Figure 1 u Updating predictions using automatons: Yeh&Patt Figure 2

n Three different flavors u Global History Register and Global Pattern History Table (GAg) u Per-address Branch History Table and Global Pattern History Table (PAg) u Per-address Branch History Table and Per-address Pattern History Tables (PAp)

Correlating branch predictors:

 - DSUBUI R3,R1,# code example 

• if (aa == 2) BNEZ R3,L
  • aa = 0; DADD R1,R0,R
• if (bb == 2) L1: DSUBUI R3,R2,#
  • bb = 0; BNEZ R3,L
• if (aa != bb) { DADD R2,R0,R - L2: DSUBU R3,R1,R - BEQZ R3,L

Two-Level Adaptive Branch

Prediction: Discussion

n Cost-effectiveness of three flavors u GAg has too much branch interference, needs long history u PAp needs lots of space for Per-address PHT u PAg is the most cost-effective

n Context switch u GAg almost unaffected u PAg, PAp degraded u Pros and cons for saving branch history on a context switch?

Other Branch Prediction

Strategies

n McFarling’s Paper: u Bimodal Predictor: Figure 1 u PAg and GAg: Figure 4 and 6 u Global Predictor with Index Selection: Figure 8 u Global History with Index Sharing (GShare): Figure 10

n Using perceptrons instead of 2-bit saturating counters Ø Jimenez&Lin’s paper (skim, not in exam) Ø Provides higher prediction accuracy

Branch Target Buffer (BTB)

n A cache that stores branch targets

n Accessed by the address of the instruction currently fetched

n Allows branch target to be read in the IF stage u When a branch is predicted taken, the fetch of the instruction at the branch target address can proceed immediately in the next cycle u Stall cycles that would have been needed to wait for the decoding of the branch and the computation of the target are saved

Branch target buffer

Return address stack

n A small address buffer organized as a stack

n When a Call is encountered the Return address (which is Call address + 4) is pushed onto the RAS

n When a Return instruction is encountered, the address from the top of the RAS is popped and used as the target

Reading Assignment

n Eric Rotenberg et al., “Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching,” MICRO 1996 (Review)

n Daniel Jimenez and Calvin Lin, “Dynamic Branch Prediction with Perceptrons,” HPCA 2001 (Skim)