Branch Prediction Techniques in Computer Architecture: ECE 4100/6100 Fall 2003 - Prof. Sud, Assignments of Computer Architecture and Organization

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ECE 4100/6100: Yalamanchili

Fall 2003

Module 3: Branch PredictionModule 3: Branch Prediction

Fall 2003^

Control Dependencies

-^ Control^

dependencies

determine

execution

order^ of

instructions^ –^ Instructions are control dependent on a branch instruction • Why do we conserve control dependencies?^ –^ Correctness^ –^ Exception behavior and dataflow • Goal: Maximize utilization of instruction fetch bandwidth

Æ

Structural branch prediction – How do we improve prediction accuracy and reduce penalties?

DependenciesData NameControl Anti^ Output

Fall 2003^

Branch Prediction

-^ Dominated

by^ history-based

predictorsÆ

past^ behavior

is^ a^ good

indicator of future behavior? • Design issues^ –^ How is history maintained?^ –^ How are decisions made based on the this history? • Significant analysis of the behavior of benchmarks is used in the designof predictors

ECE 4100/6100: S. Yalamanchili

Fall 2003^

Dynamic Branch Prediction Strategies • Use history of behavior, taken vs. not-taken, by a single branch • Predict the next decision that will be taken by this branch, i.e.,taken vs. not-taken • A general model (shown above) captures history and uses it tomake predictions

…^

0 n-

prediction

Last branch behavior,i.e., taken or not taken From Ref: “Modern Processor Design: Fundamentals ofSuperscalar Processors, J. Shen and M. Lipasti Shift register How do we capturethis history?How do we predict?

Fall 2003^

Correlating Predictions Across Multiple Branches • Instead of having a predictor for a single branch have a predictor forthe most recent history of branch decisions • For each branch history sequence, use an

Correlating across twosuccessive branches^ n -bit predictor

Fall 2003^

Performance Comparison

-^ Size^ and

resolution ofpredictors^ establishedempirically

Fall 2003^

Misprediction Recovery

-^ What actions must be taken on a misprediction?^ –^ Remove “predicted” instructions^ –^ Start fetching from the correct branch target(s) •^ What information is necessary to recover from misprediction?^ –^ Address information for non-predicted branch target address^ –^ Identification of those instructions that are “predicted”^ –^ To be invalidated and prevented from completion^ –^ Association between “predicted” instructions and specific branch^ –^ When that branch is mispredicted then only those instructions mustbe squashed

Fall 2003^

Branch Target Buffers

-^ Store the branch instruction address (PC) and correspondingtarget address in a small associative cache^ –^ Miss on the first access to a branch instruction •^ Access in parallel with instruction cache^ –^ Hit produces the branch target address

Class Administration

 - Fall 

• • Midterms: September
• th , 2003 and November
• th , - • Assignment 1: Posted September - th , - Due September - th , - • Assignment 2: Posted September - th , - Due October - th, - • Assignment 3: Posted October - th , - Due October - th , - • Final Assignment/Project: Posted November - th , - Due December - nd ,

ECE 4100/6100: S. Yalamanchili

Fall 2003^

Further Analysis

-^ Even with accurate branch prediction, through multiple targets,we must fetch instructions from multiple targets^ –^ What

is^ the^ effect

on^ instruction

bandwidth^

and^ pipeline

performance? – How can we increase instruction fetch bandwidth to compensate – Assume perfect branch prediction

B^

B B^

B^

B Instructions are located at B different cache lines

Exploit instruction locality + branch prediction

!

Fall 2003^

The Trace Cache: Principle

-^ Store recurring sequences of basic blocks^ –^ These form a contiguous sequence of instructions

Æ^ “big” basic

block – Issue multiple instructions from this “big” basic block

Æ^ high

B1^ issue rate • Trace length determined by (#instructions, #branches) • Predict and fetch traces rather than lines in the instructioncache – Multiple instructions are issue from the trace B^

B1^ B^

B2^ B

Branch instruction^

Branch instruction^

Branch instruction

Instruction trace

Fall 2003^

The Trace Cache

-^ Read pages 1-12 of the handout and pg. 447-448 •^ Capture/fill trace history •^ Parallel look-up of trace history and instruction cache^ –^ First address + branch prediction bits to index the cache •^ Ref: E. Rotenberg, S. Bennet, and J. Smith, “Trace Cache: A LowLatency^

Approach^ to

High^ Bandwidth

Instruction^

Fetching,”^29

th

Annual International Symposium on Microarchitecture

branchpredictor , Dec. 1996. TraceFetchlogic

n instructions^

n instructions

FetchaddressTrace cache

I-cache

Fall 2003^

Concluding Remarks

-^ Challenge

to^ keeping

the^ execution

core^ fed^

is^ handling

control flow • Prediction^

and^ recovery

mechanisms

key^ to^ keeping

the

pipeline active • Superscalar datapaths provide increased pressure pushing forbetter,^ more

innovative

techniques

to^ keep^

pace^ with

technology-enabled appetite for instruction level parallelism • What next?