Homework 4
CDA 5155: Fall 2008
Due Date: 12/04/2008 11:59 PM (UF EDGE Students: 12/11/2008 11:59 PM)
Primary TA: Weixun Wang
Brief Solution
You are not allowed to take or give help in completing this assignment. Submit the PDF version of
the submission in e-Learning website before the deadline. Please include the sentence in bold on
top of your submission: “I have neither given nor received any unauthorized aid on this
assignment”.
Problem 1
1. [5] 2 + 1 + 2 * (N – 1) = 2N + 1
The first access of X by each processor results in a cache miss, i.e. the first two instructions in
iteration 1. In the third instruction, P2 generates an invalidation because of which P1 suffers a
miss in the fourth instruction. In the next (N – 1) iterations, P1 generates an invalidation because
of which P2 suffers a miss and then P2 generates an invalidation because of which P1 suffers a
miss.
2. [5] 2
The first access of X by each processor results in a cache miss. In all subsequent iterations, no
more cache miss will occur due to broadcasting. Therefore, number of misses is 2.
Problem 2
1. [5]
Lock: LOAD R2, 0(R1)
BNEZ R2, Lock
ADDUI R2, R0, #1
EXCH R2, 0(R1)
BNEZ R2, Lock
Spin on regular lock (LD) is a read operation on the block. It does not need invalidate other copies
of the block in other processor’s caches.
2. [5]
Lock: LL R2, 0(R1)
BNEZ R2, Lock
ADDUI R2, R0, #1
SC R2, 0(R1)
BNEZ R2, Lock
