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Homework 4
CDA 5155: Fall 2008
Due Date: 12/04/2008 11:59 PM (UF EDGE Students: 12/11/2008 11:59 PM)
Primary TA: Weixun Wang
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Problem 1 Consider two processors P1 and P2. Suppose the program reference stream is as follows: Repeat N times { P1 writes variable X; P2 reads variable X; P2 writes variable X; P1 reads variable X; }
Assume that the caches are initially empty in both processors and a write-allocate policy is used.
- [5] Write the expression (using N) for the number of cache misses for the above reference stream with the basic invalidate-based write-back cache coherence protocol discussed in the class (Slide 17 in multiprocessor.ppt). A request made only for an invalidation does not count as a miss. Please explain how you got the expression.
- [5] Write the expression for the number of cache misses for the reference stream in Part 1 with an update-based (write broadcast) cache coherence protocol (Slide 17 in multiprocessor.ppt). Please explain how you got the expression.
Problem 2 As discussed in class, the atomic exchange instruction, EXCH R2, 0(R1), exchanges the content of R2 with the content in memory location M[0(R1)] as an atomic operation. This EXCH instruction involves both a read and a write memory operation and is often used to implement a spin lock as follows: ADDUI R2, R0, #1 ; R2=
Lock: EXCH R2, 0(R1)
BNEZ R2, Lock
Unlock: SD R0, 0(R1) ; update M[0(R1)] = 0
The implementation of the EXCH is usually integrated with the hardware cache coherence mechanism. In this problem a write-invalidate, ESI (Snoopy with Exclusive, Shared, Invalid) coherence protocol is used. Therefore, the write operation in EXCH requires the Exclusive state of the block and causes invalidations to other copies of the block located in other caches. A more efficient spin lock is to spin on regular load (LD) instruction instead of spinning on EXCH.
An alternative approach to implement an atomic EXCH is to use a pair of special Load Linked (LL) and Store Conditional (SC) instructions. These two instructions are always used in order with LL followed by SC. If the content of the memory location specified by LL is changed between the LL and SC, then the SC fails without updating the memory. After executing the SC, R3=1 if the exchange is successful, or R3=0 if M[0(R1)] has been modified between the pair of LL and SC.
- [5] Please rewrite the above code using (spinning on) regular load (LD) instead of EXCH and briefly explain why spin on regular load is more efficient.
- [5] Rewrite the above code using Load Linked (LL) and Store Conditional (SC) instead of EXCH.
- [6] Assume that there are 4 processors. P0 owns a lock (specified at location M[0(R1)]) and is in the critical section. P1, P2, and P3 are all spinning on the Lock code competing for the lock. The block containing the lock variable is shared in all caches. Now, P0 releases the lock by updating the lock variable to 0 using SD R0, 0(R1) and cause coherence invalidations. Afterwards, P1 wins the lock and enters the critical section, while both P2 and P3 must spin again.
List all the memory requests and cache coherence transactions starting when P0 releases the lock to the steady state when P1 is in critical section and both P2 and P3 are spinning on lock variable located in their local caches. You need to list the memory requests and coherence transactions using EXCH instruction in table like the following on your answer sheet. Note that each coherence transaction can take multiple cycles. Also, your answer does not need to fill all the rows in the table.
- [9] A general organization of a Chip-Multiprocessor (CMP) with four cores is shown below. Various ways to construct the components inside the CMP are possible.
Few likely options are listed below. Fill in the table by selecting these options that achieve the goal and explain the reasons. (Note, in Exclusive L1/L2, no data block can exist in both L1 and L2.)
L1 organization: Private L1 (the only option) L2 organization: Private L2; Shared L Inclusion property: Inclusive L1/L2; Exclusive L1/L Cache coherence: Snooping-bus mechanism; Directory-based mechanism
Goal Options needed Reason
Maximum memory hierarchy capacity
Minimum L2 access time
Implement On-Chip directory-based coherence scheme
Problem 4 Assume that we have a Snoppy invalidation-based cache coherence protocol in which there are the following three states: Modified: You have modified the data block, holding the most recent, correct copy of the data and no other processor has a copy. Shared: You have a copy of data that another processor also has. Invalid: Your copy of the data is not up to date.
In alternative cache coherence protocol designs, we have other states including:
Exclusive: You are the sole owner of the data and are free to modify it without a bus invalidate message. Owner: Your data is shared, but you have the master copy in your cache, which means you are the one who made the latest update of that data.
- [7] In this new 5-state MEOSI cache coherence protocol, please specify the actions (from processor or bus) that trigger the following seven state transitions: a) Invalid โ Modified b) Invalid โ Shared c) Invalid โ Exclusive d) Shared โ Modified e) Exclusive โ Modified f) Modified โ Owned g) Owned โ Modified
- [3] Describe and compare MESI and MOESI cache coherence protocols. Which one is better in designing future Chip Multiprocessor (CMP) with multiple-level on-chip caches and why?
