331 W10.1 Spring 2005
14:332:331
Computer Architecture and Assembly Language
Spring 2005
Week 10
Building a Multi-Cycle Datapath
[Adapted from Dave Patterson’s UCB CS152 slides and
Mary Jane Irwin’s PSU CSE331 slides]
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Multicycle MIPS Datapath Implementation, Study notes of Electrical and Electronics Engineering
An in-depth analysis of the multicycle mips datapath implementation, discussing its advantages over the single cycle datapath, the high-level view of the multicycle datapath, clocking the multicycle datapath, and breaking up instructions into steps. It also covers instruction fetch, instruction decode and register fetch, r-type instruction execution, memory read access, memory write completion, and memory read completion.
Typology: Study notes
Pre 2010
1 / 31
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download Multicycle MIPS Datapath Implementation and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!
Spring 2005
Computer Architecture and Assembly Language
Spring 2005
Week 10
Building a Multi-Cycle Datapath
[Adapted from Dave Patterson’s UCB CS152 slides and
Mary Jane Irwin’s PSU CSE331 slides]
Spring 2005
Head’s Up
This week’s material
z
Multicycle MIPS datapath implementation
Reading assignment – PH 5.5 and C.
Spring 2005
Disadvantages of the Single Cycle Datapath
Uses the clock cycle inefficiently – the clock cyclemust be timed to accommodate the slowestinstruction
z
especially problematic for more complex instructions likefloating point multiply
Is wasteful of area since some functional unitsmust be duplicated since they can not be “shared”during an instruction execution
z
e.g., need separate adders to do PC update and branchtarget address calculations, as well as an ALU to do R-type arithmetic/logic operations and data memoryaddress calculations
Spring 2005
Multicycle Implementation Overview
Each step in the execution takes 1 clock cycle
An instruction takes more than 1 clock cycle tocomplete
Not every instruction takes the
same
number of clock
cycles to complete
Multicycle implementations allow
z
functional units to be used more than once per instructionas long as they are used on different clock cycles, as aresult
only need one memory
need only one ALU/adder
z
faster clock rates
z
different instructions to take a different number of clockcycles
Spring 2005
Clocking the Multicycle Datapath
Address
Read Data
(Instr. or Data)
Memory
PC
Read Addr 1Read Addr 2Write Addr Write Data
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IR
MDR
A B
ALUout
System Clock
MemWrite
RegWrite
clock cycle
Spring 2005
Break up the instructions into steps where eachstep takes a cycle while trying to
z
balance the amount of work to be done in each step
z
restrict each cycle to use only one major functional unit
At the end of a cycle
z
Store values needed in a later cycle by the currentinstruction in a state element (internal register) not visibleto the programmer
IR – Instruction RegisterMDR – Memory Data RegisterA and B – register file read data registersALUout – ALU output register
z
All (except IR) hold data only between a pair of adjacentclock cycles (so don’t need a write control signal)
z
Data used by subsequent instructions are stored inprogrammer visible state elements (i.e., register file, PC, ormemory)
Multicycle Approach
Spring 2005
Reading/writing to
z
any of the internal registers or the PC occurs (quickly) atthe end of a clock cycle
z
reading/writing to the register file takes ~50% of a clockcycle since it has additional control and access overhead(reading can be done in parallel with decode)
Have to add multiplexors in front of several of thefunctional unit inputs because the functional unitsare shared by different instruction cycles
All operations occurring in one step occur in parallelwithin the same clock cycle
z
This limits us to one ALU operation, one memory access,and one register file access per step (per clock cycle)
Multicycle Approach, con’t
Spring 2005
Instruction Fetch
Instruction Decode and Register Fetch
R-type Instruction Execution, Memory Read/WriteAddress Computation, Branch Completion, or JumpCompletion
Memory Read Access, Memory Write Completion orR-type Instruction Completion
Memory Read Completion (Write Back)
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
Five Instruction Steps
Spring 2005
Fetch Control Signals Settings
Start
Instr Fetch
Spring 2005
Don’t know what the instruction is yet, so can only
z
Read registers rs and rt in case we need them
z
Compute the branch address in case the instruction is abranch
RTL:^ A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC +(sign-extend(IR[15-0])<< 2);
Note we aren't setting any control lines based onthe instruction (since we are busy "decoding" it inour control logic)
Step 2: Instruction Decode and Register Fetch
331 W10.
Spring 2005
Decode Control Signals Settings
Start
Instr Fetch
Decode
Unless otherwise assigned
PCWrite,IRWrite,MemWrite,RegWrite=0others=X
IorD=
MemRead;IRWrite
ALUSrcA=
ALUsrcB=
PCSource,ALUOp=
PCWrite
Spring 2005
ALU is performing one of four functions, based oninstruction type
Memory reference (lw and sw):
ALUOut = A + sign-extend(IR[15-0]);
R-type:
ALUOut = A op B;
Branch:
if (A==B) PC = ALUOut;
Jump:
PC = PC[31-28] || (IR[25-0] << 2);
Step 3 (instruction dependent)
331 W10.
Spring 2005
Execute Control Signals Settings
Start
Instr Fetch
Decode
Execute
(Op
= R-type)
(Op = beq)
(Op = lw
or
sw)
(Op = j)
Unless otherwise assigned
PCWrite,IRWrite,MemWrite,RegWrite=0others=X
ALUSrcA=
ALUSrcB=
ALUOp=
PCWriteCond=
IorD=
MemRead;IRWrite
ALUSrcA=
ALUsrcB=
PCSource,ALUOp=
PCWrite
Spring 2005
Step 4 (instruction dependent)
Memory reference:
MDR = Memory[ALUOut];
-- lw
or
Memory[ALUOut] = B;
-- sw
R-type instruction completion
Reg[IR[15-11]] = ALUOut;