Chapter 5.1 - Processor Design 1 1
Outline of These Slides
•Overview
•Design a processor: step-by-step
•Requirements of the instruction set
•Components and clocking
•Assembling an adequate Data path
•Controlling the data path
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Understanding Datapath & Control in Single Cycle Processor Design, Slides of Assembly Language Programming
An in-depth analysis of single cycle processors, focusing on the roles of datapath and control. It covers the requirements of the instruction set, components of the datapath, and the importance of clocking. The document also discusses the concept of memory hierarchy and sequential logic.
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Chapter 5.1 - Processor Design 1
Outline of These Slides
•^ Overview •^ Design a processor: step-by-step •^ Requirements of the instruction set •^ Components and clocking •^ Assembling an adequate Data path •^ Controlling the data path
Chapter 5.1 - Processor Design 1
The Big Picture: Where Are We Now?
-^ The five classic components of a computer •^ Today’s topic: design a single cycle processor
ControlDatapath
Memory
Processor
Input Output
inst. set design
technology
machinedesign
Arithmetic
Chapter 5.1 - Processor Design 1
Big Picture: The Performance Perspective•^
Performance of a machine is determined by:
- Instruction count– Clock cycle time– Clock cycles per instruction -^ Processor design (datapath and control) will determine: - Clock cycle time– Clock cycles per instruction -^ What we will do Today: - Single cycle processor: -^
Advantage: One clock cycle per instruction
-^
Disadvantage: long cycle time
CPI
Inst. Count
Cycle Time
Chapter 5.1 - Processor Design 1
How to Design a Processor: Step-by-step
-^ 1. Analyze instruction set
datapath requirements
- the meaning of each instruction is given by the
register transfers
- datapath must include storage element for ISA registers -^
possibly more
- datapath must support each register transfer -^ 2. Select set of datapath components and establish clockingmethodology •^ 3. Assemble datapath meeting the requirements •^ 4. Analyze implementation of each instruction to determine setting ofcontrol points that effects the register transfer. •^ 5. Assemble the control logic
Chapter 5.1 - Processor Design 1
Step 1a: The MIPS-lite Subset for Today•^
ADD and SUB
- addU rd, rs, rt– subU rd, rs, rt -^ OR Immediate: - ori
rt, rs, imm
-^ LOAD / STORE Word - lw rt, rs, imm16– sw rt, rs, imm -^ BRANCH: - beq rs, rt, imm
op^
rs^
rt^
rd^
shamt
funct
0
6
11
16
21
26
31
6 bits
6 bits
5 bits
5 bits
5 bits
5 bits
op^
rs^
rt^
immediate
0
16
21
26
31
6 bits
16 bits
5 bits
5 bits
op^
rs^
rt^
immediate
0
16
21
26
31
6 bits
16 bits
5 bits
5 bits
op^
rs^
rt^
immediate
0
16
21
26
31
6 bits
16 bits
5 bits
5 bits
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Chapter 5.1 - Processor Design 1
Logical Register Transfers
-^ Register Transfer Logic gives the meaning of the instructions •^ All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ]op | rs | rt |
Imm
= MEM[ PC ]
inst
Register Transfers
ADDU
R[rd]
R[rs] + R[rt];
PC
PC + 4
SUBU
R[rd]
R[rs] – R[rt];
PC
PC + 4
ORi
R[rt]
R[rs] | zero_ext(Imm16);
PC
PC + 4
LOAD
R[rt]
MEM[ R[rs] + sign_ext(Imm16)];
PC
PC + 4
STORE
MEM[ R[rs] + sign_ext(Imm16) ]
R[rt];
PC
PC + 4
BEQ
if ( R[rs] == R[rt] ) then PC
PC + 4 + sign_ext(Imm16)] || 00
else PC
PC + 4
Chapter 5.1 - Processor Design 1
Step 2: Components of the Datapath•^
Combinational Elements • Storage Elements
- Clocking methodology
Chapter 5.1 - Processor Design 1
Combinational Logic Elements (Basic Building Blocks)
-^ Adder •^ MUX •^ ALU
A B
SumCarry
A B
Result
OP
A B^
Y
Select
CarryInAdder MUX ALU
Chapter 5.1 - Processor Design 1
Storage Element: Idealized Memory
-^ Memory (idealized) - One input bus: Data In– One output bus: Data Out -^ Memory word is selected by: - Address selects the word to put on Data Out– Write Enable = 1: address selects the memoryword to be written via the Data In bus -^ Clock input (CLK) - The CLK input is a factor ONLY during write operation– During read operation, behaves as a combinational logic block:
•^
Address valid
Data Out valid after “access time.”
Clk
Write EnableData In
DataOut
Address
Chapter 5.1 - Processor Design 1
Memory Hierarchy (Ch. 7)
•^ Want a single main memory, both large and fast •^ Problem 1: large memories are slow while fastmemories are small
-^ Example: MIPS registers (fast, but few)
•^ Solution
: mix of memories provides illusion of single
large, fast memory
-^ Cache: a small, fast memory; Holds a copy of part of a larger,slower memory •^ Imem, Dmem are really separate caches memories
Chapter 5.1 - Processor Design 1
Adding a Clock to a Circuit
•^ Clock: free running signal with fixed
cycle time
( clock
period
period
rising edge
falling edge
high (1)low (0)^ °^ Clock determines
when
to write memory element
-^ level-triggered - store clock high (low) •^ edge-triggered - store only on clock edge °^ We will use negative (falling) edge-triggered methodology
Chapter 5.1 - Processor Design 1
Role of Clock in MIPS Processors• single-cycle machine: does everything in oneclock cycle^ •^
instruction execution = up to 5 steps • must complete 5th step
before
cycle ends
clocksignal
instruction execution
step 1/step 2/step 3/step 4/step 5
datapathstable
falling clock edge register(s)written
rising clock edge
Chapter 5.1 - Processor Design 1
SR-Latches
-^ SR-latch with NAND Gates, also known as
S ´
R ´^
-latch
-^ S = 0 and R = 0 not allowed^ °^
Symbol for SR-Latch with NAND gates
Chapter 5.1 - Processor Design 1
SR-Latches with Control Input
-^ SR-latch with NAND Gates and control input
C
°^ C
= 0, no change of state;
°^ C
= 1, change is allowed;^ •^
If^
S^ = 1 and
R
= 1,
Q
and
Q