L14 – Building a Beta 1
6.004 – Spring 2009 3/31/09
Building the Beta
Lab #5 due Thursday
L14 – Building a Beta 2
6.004 – Spring 2009 3/31/09
CPU Design Tradeoffs
Minimum Cost : measured by the size
of the circuit.
Best Performance/Price: measured by the
ratio of MIPS to size. In power-sensitive
applications MIPS/Watt is important too.
Maximum Performance: measured by the
numbers of instructions executed per
second
L14 – Building a Beta 3
6.004 – Spring 2009 3/31/09
Performance Measure
MIPS = Clock Frequency (MHz)
C.P.I.
Millions of Instructions per Second
Clocks per instruction
PUSHING PERFORMANCE ...
TODAY: 1 cycle/inst.
LATER: more MHz via pipelining
L14 – Building a Beta 4
6.004 – Spring 2009 3/31/09
The Beta ISA
Instruction classes
distinguished by
OPCODE:
OP
OPC
MEM
Transfer of Control
OpCode
6
Operate class: Reg[Rc] Reg[Ra] op Reg[Rb]
6 555 11
Ra Rc Rb (UNUSED)
01XXXX
Operate class: Reg[Rc] Reg[Ra] op SXT(C)
16
Ra Rc Literal C (signed) 11XXXX
Opcodes, both formats:
ADD SUB MUL* DIV* *optional
CMPEQ CMPLE CMPLT
AND OR XOR
SHL SHR SRA
LD: Reg[Rc] Mem[Reg[Ra]+SXT(C)]
ST: Mem[Reg[Ra]+SXT(C)] Reg[Rc]
JMP: Reg[Rc] PC+4; PC Reg[Ra]
BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C)
BNE:
LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)]
Reg[Rc] PC+4; if Reg[Ra]0 then PC PC+4+4*SXT(C)
Ra Rc Literal C (signed) 10XXXX
Figure by MIT OpenCourseWare.
