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L05 – Sequential Logic 1
2/19/
Sequential Logic:^ adding a little
state
Lab
is due^ tonight (checkoff meeting by next Thursday).
modified 2/17/09 10:
QUIZ #1 Tomorrow! (covers thru L4/R5)
L05 – Sequential Logic 2
6.004 – Spring 2009
2/19/
6.004: Progress so far…
01101
PHYSICS: Continuousvariables, Memory, Noise,f(RC) = 1 - e
-t/RC^
COMBINATIONAL: Discrete,memoryless, noise-free,lookup table functions
2.71354 volts
C^ B^ A^ Y 0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
What otherbuildingblocks do weneed in orderto compute?
L05 – Sequential Logic 3
2/19/
Something We Can’t Build (Yet)
What if you were given the following design specification:
When the button is pushed:1) Turn on the light ifit is off2) Turn off the light ifit is onThe light should changestate within a secondof the button press button^
light
What makes this circuit so differentfrom those we’ve discussed before?
1. “State” – i.e. the circuit has memory2. The output was changed by a input“event” (pushing a button) ratherthan an input “value”
L05 – Sequential Logic 4
6.004 – Spring 2009
2/19/
Digital State One model of what we’d like to build
Plan: Build a Sequential Circuit with stored digital STATE –^ • ^ Memory stores CURRENT state, produced at output^ • ^ Combinational Logic computes
- ^ NEXT state (from input, current state) • ^ OUTPUT bit (from input, current state) • State changes on LOAD control input
CombinationalLogic
CurrentState
NewState
Input^
Output
MemoryDeviceLOAD
L05 – Sequential Logic 5
2/19/
Needed:
Storage
Combinational logic is
stateless
valid outputs always reflect current inputs.To build devices with state, we need components which
store
information (e.g., state) for subsequent access.^ ROMs^
(and other combinational logic) store information “wired in” to theirtruth table Read/Write^ memory elements are required to build devices capable ofchanging their contents.
How can we store – and subsequently access -- a bit?^ • ^ Mechanics: holes in cards/tapes^ • ^ Optics: Film, CDs, DVDs, …^ • ^ Magnetic materials^ • ^ Delay lines; moonbounce^ • ^ Stored charge
L05 – Sequential Logic 6
6.004 – Spring 2009
2/19/
Storage: Using Capacitors
We’ve chosen to encode information using voltages and we knowfrom 6.002 that we can “store” a voltage as charge on a capacitor:
Pros:^ ^ compact – low cost/bit(on BIG memories)Cons:^ ^ complex interface^ ^ stable? (noise, …)^ ^ it leaks!
^ refresh
N-channel fet servesas access switchTo write:Drive bit line, turn on access fet,force storage cap to new voltageTo read:precharge bit line, turn on access fet,detect (small) change in bit line voltage
word line V^ REF
Bitline
Suppose we refreshCONTINUOUSLY?
L05 – Sequential Logic 7
2/19/
Storage: Using Feedback
IDEA: use positive feedback to maintain storage indefinitely.Our logic gates are built to restore marginal signal levels, sonoise shouldn’t be a problem!
V^ IN^
VOUT
Result: a bistablestorage element
Feedback constraint:V^ = VIN^
OUT VTC forinverter pair
VIN
VOUT^
Three solutions:^ ^ two end-points are stable^ ^ middle point is unstable
Not affectedby noise We’ll get back to this!
L05 – Sequential Logic 8
6.004 – Spring 2009
Y 2/19/
B S
Settable Storage Element
It’s easy to build a settable storage element (called a latch)using a
lenient
MUX: 0 1
GD 0 -- 0 -- 10 11
Q^ QIN^01 -- --
“state” signalappears as bothinput and output OUT 0 1 0 1
Q stableQ follows D
A D G
Here’s a feedback path,so it’s no longer acombinational circuit. Q
L05 – Sequential Logic 13
6.004 – Spring 2009
2/19/
Combinational Cycles
CombinationalLogic
D^ Q G
CurrentState
NewState
Input^
Output
When G=1, latch is
Transparent…
… provides a combinational path from D to Q.Can’t work without tricky timing constrants on G=1 pulse: • ^ Must fit within contamination delay of logic • ^ Must accommodate latch setup, hold times Want to signal an INSTANT, not an INTERVAL…
Looks like a stupidApproach to me…
L05 – Sequential Logic 14
6.004 – Spring 2009
2/19/
Flakey Control Systems
Here’s a strategyfor saving 3 buckson the SumnerTunnel!
L05 – Sequential Logic 15
6.004 – Spring 2009
2/19/
Escapement Strategy
The Solution:Add two gates^ and only openone at a time.
L05 – Sequential Logic 16
6.004 – Spring 2009
2/19/
Edge-triggered Flip Flop
D^ Q G
D^ Q^ G
D^ Q
D CLK
Q^
D CLK
Q
master^
slave
Observations:^ ^ only one latch “transparent” at any time:
^ master closed when slave is open ^ slave closed when master is open ^ no combinational path through flip flop Q only changes shortly after 0
^1
transition of CLK, so flip flop appearsto be “triggered” by rising edge of CLK
The gate of thislatch is open whenthe clock is low
The gate of thislatch is open whenthe clock is high
What doesthat one do? D^00 Q^11 SG
(the feedback path in one of the master or slave latches is always active)
Transitions mark instants, not intervals
Figure by MIT OpenCourseWare.
Figure by MIT OpenCourseWare.
L05 – Sequential Logic 17
2/19/
Flip Flop Waveforms
D^ Q G
D^ Q^ G
D^ Q
D CLK
Q^
D CLK
Q
master^
slave
D CLK Q master closedslave open
slave closedmaster open
L05 – Sequential Logic 18
6.004 – Spring 2009
2/19/
Um, about that hold time…
D^ Q G
D^ Q G
D^
Q
master^
slave
CLK
Consider HOLD TIME requirement for slave
0) clock transition
^ slave freezes data:
- SHOULD be no output glitch, since master held constant data; BUT• master output contaminated by change in G input!• HOLD TIME of slave not met, UNLESS we assume sufficientcontamination delay in the path to its D input!
Accumulated t
thru inverter, GCD
^ Q path of master must cover
slave t
for this design to work!HOLD
The master’s contaminationdelay must meet the holdtime of the slave
L05 – Sequential Logic 19
2/19/
Flip Flop Timing - I
Q CLK D
D^ QD
CLK
Q
<tPD
t: maximum propagation delay, CLKPD
Q
>tCD
t: minimum contamination delay, CLKCD^
Q
>tSETUP
t: setup timeSETUP^^ guarantee that D has propagated through feedback path before master closes
>tHOLD
t: hold timeHOLD^^ guarantee master is closed and data is stable before allowing D to change
L05 – Sequential Logic 20
6.004 – Spring 2009
2/19/
Single-clock Synchronous Circuits
Single-clock Synchronous Discipline•^ No combinational cycles^ •^ Only care about value of register datainputs just before rising edge of clock^ •^ Period greater than everycombinational delay^ •^ Change saved state after noise-inducing logic transitions havestopped!
We’ll use Flip Flops and
Registers
- groups of FFs sharing a clock
input – in a highly constrained way to build digital systems:
-^ Single clock signal shared amongall clocked devices
Does thatsymbolregister?
