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EECS 373
Lab 4: Bus Interfacing for Byte-Addressable Memory
7/29/
Schedule
See posted lab schedule for pre-lab, in-lab and post-lab due dates.slide
Objectives
The purpose of this lab is to:
- Introduce you to the mechanisms required for handling multiple data transfer sizes, including transfers smaller than the bus width.
- Help you to understand the overheads involved in handling unaligned accesses.
- Introduce you to how a simple memory structure interfaces to a bus.
Overview
This lab expands on Lab 3, adding a small memory module to your hardware design. For simplicity, in Lab 3 you assumed that any access to your I/O registers was a 32-bit access. Unlike the lab 3 I/O register, a general-purpose memory module must handle any access size the CPU may generate—byte, half-word, or word, in the case of the MPC823. Also unlike your I/O registers, your memory module will occupy a range of bus locations. As a result, your design will use different portions of the address supplied by the MPC823 for different purposes. Some of the address bits will determine whether or not your memory module is being accessed; some will determine which word within the module is being accessed; and, if the access size is less than a word, some of the address bits will determine which byte or bytes within the word are being accessed. To exercise your memory module, you will write a small program to read and write the memory using the slide switches and LED displays. You will reuse the I/O registers from your Lab 3 design to interface with the switches and LEDs.
Design Specifications
Hardware Implement a 256-byte memory module on the FPGA (using 32x8 memory parts from the device library) and interface it to the MPC823 bus. This memory should occupy 256 con- secutive byte addresses starting at address 0x3300000. The module should correctly han- dle aligned byte, halfword, and word reads and writes. (Recall that the MPC823 will only generate aligned accesses on the bus.) Your memory module should be integrated with your hardware design from Lab 3, so that your Lab 3 I/O registers can be used in conjunc- tion with the memory. Software Write an assembly-language program that lets you use the switches and LED displays on the expansion board to direct the processor to read and write your memory one byte at a time. The resulting operation is reminiscent of the front panel of several old computer models (like the DEC PDP-11 series), where a bank of toggle switches and LEDs could be used to read and write memory locations. On these old machines, the front panel switches controlled hardware that directly performed read and write transactions: the purpose of the front panel was to let users access memory even when the CPU couldn’t. For example, the front panel could be used to manually enter an instruction sequence (in binary!) to boot the
machine, or to examine memory locations to debug the system when it had crashed so hard that the CPU was not responding. Your program will be emulating this front panel operation in software by reading the switches, performing any appropriate memory accesses, and displaying the results on the LEDs. Note that, unlike the old-time front panels, the switches and LEDs will not talk directly to the memory module; although they share the same data bus, all interaction between the switches, LEDs, and memory is performed in software by the CPU. Your program must operate as follows:
- Your program must maintain a “current memory location”, which is a byte address in the range 0-255 indicating one of the 256 bytes in your memory module. (0 is 0x3300000, 255 is 0x33000FF) The current memory location should be set to 0 ini- tially.
- At all times, the bar-graph display indicates the address of the current memory loca- tion in binary, and the seven-segment display indicates the byte value stored at the cur- rent memory location.
- When pushbutton S0 (BTN0) is pressed, the binary value entered on the slide switches should be written to the current memory location.
- When pushbutton S1 (BTN1)is pressed, the current memory location address should be changed. The new current memory location is determined by pushbutton S (BTN2) and S3 (BTN3), as specified in Table 1.
Design Notes and Hints
- Review your lecture notes on bus transfer sizing. Read Section 13.4.5 of the PowerPC MPC823 User’s Manual.You may assume you are using a 32 bit data port. Pay partic- ular attention to Figure 13-18, Table 13-2, and Table 13-4 on page 13-33.
- As in Lab 3, you should check only the upper six external address lines (A[6:11]) to determine whether your memory module is being accessed. Of course, you will also have to examine some low-order address lines to determine which location in your memory module is being accessed.
- Use the RAM32x8S part from the Xilinx library. Each part is equivalent to 256 D flip- flops in an array of 32 rows and 8 columns. The five address inputs select one of the 32 rows. The eight Q outputs reflect the values stored in the eight flipflops of the selected row.
- You should construct a 128-byte (32-word) memory module (ISE custom symbol) using four of the RAM32x8S parts. This module should use four independent byte- enable inputs to control access size, as discussed in lecture. Define this module as a Xilinx custom symbol.
- Construct your 256-byte module by combining two of your 128-byte modules. You may want to sketch this top-level design first to help you figure out exactly which inputs and outputs you need to provide on the 128-byte module design.
Table 1: Effect of S2 & S3 on current memory location.
PB S2 SPB S3 New current location
(either) pressed value on slide switches
pressed (either) (current location – 1) mod 256
not pressed not pressed (current location + 1) mod 256
lbz r5, 5(r3) stb r5, 1(r3) lhz r6, 0(r3) lhz r7, 1(r3) lhz r8, 3(r3) lwz r9, 0(r3) lwz r10, 1(r3) stw r10, 3(r3) lwz r11, 2(r3)
a. List the values of registers r4 through r11 after executing the fragment. ( 8 points )
b. Which (if any) of these instructions cause unaligned accesses? ( 3 points )
c. For the following instructions, complete the table listing the sequence of bus accesses. Assume r3 = 0x02900000, r4 = 0x11223344, r5 = 0x 02900008, 0x 02900008 = 0x55667788 and 0x290000c = 0xaabbccdd. The instructions exe- cute independently of one another. Space is provided for three cycles whether needed or not. The first entry is an example. Use - for unknown values..( 6
points)
Instruction Access Cycle
TSIZE Address Bus Contents
Data Bus Contents
stw r4, 2(r3) 1 0x0290 0002 0x
2 0x0290 0004 0x3344----
stw r4, 3(r3)
stb r4, 3(r3)
lwz r4, 3(r5)
lwz r4, 1(r5)
lhz r4, 1(r5)
Group Pre-lab Assignment
- Fill out Table 3 at the end of the lab document. ( 3 points)
- Submit either a hand drawn or sufficiently large Xilinx schematic showing all your data paths between the memory, switches and LEDs and the processor connections. Label all data paths with bus names. All devices may be shown as custom symbols or boxes. It is not necessary to show control signal paths. On the data paths, indicate where TriState buffers are required. ( 3 points) 3. Design a memory write decoder that provides the appropriate byte enables for byte 0-3, half word and word writes for a 32 bit data port. Table 13-3 of the White Book shows the external bus contents for the various write combinations. Be careful, Table 13-3 shows the contents of the external data bus for 8, 16 and 32 bit data ports. Sub- mit a simulation of your decoder showing the combinations for TSIZE, A30 and A31 listed in Table 13-3 with the appropriate byte enables activated. Include a sche- matic or HDL listing of your decoder. ( 3 points)
In-Lab Procedure
Part I: Debugging the Memory Module
- Partitioning and testing your design is very important in this lab since your design now consists of several devices. Testing the hardware with SingleStep read write commands thru the command window is essential before integrating the software.
- You can start by testing the your byte enable logic with the simulator to be sure it corresponds to byte, half word and word transactions appropriately.
- Although it is possible to simulate the memory modules, it is probably more produc- tive to debug on the kit using the logic analyzer.
- It can be beneficial to isolate the memory from other IO by simply disabling it. For example, disable the tristate buffer to the switches when read testing the memory with read command lines in SingleStep.
- One of the most difficult problems debugging a read/write register is to determine if it is the read or the write that is the problem. Consider the following debug methods:
a. First, hardwire the address lines to a fixed address (i.e. the first location). In this way you will know you are always accessing the same address for any transac- tion.
b. To test the write path, hardwire a fixed value to the data path into the memory module. Make a simple bus test module that has an output bus with a known value. Disconnect the data path from the processor and connect your known value module to the input of the module.
c. Similarly, to test the read path, disconnect the memory module for the data path from to the processor and connect the bus test module in its place.
d. Be sure to observe all relevant logic control signals and address and data buses with the logic analyzer for the transaction in question.
- Remember the SingleStep read write commands can be configured for byte, half word and word transactions. Type Help in the command window then the command in question if you need to remember the details. For example, Help read.
- Report your observations from demonstration 1.4. What are the data values and size codes for each transaction. How many bus transactions are necessary? ( 8 points )
- The MPC823 reduces every unaligned memory access to a sequence of aligned bus transactions. If we remove the restriction that bus transactions must be aligned, some unaligned memory accesses could be completed in fewer transactions ( without mod- ifying your memory module to read multiple words in one transaction). ( 10 points )
a. Which (if any) unaligned half-word accesses could be performed in fewer trans- actions?
b. Which (if any) unaligned word accesses could be performed in fewer transac- tions. What changes would be required to the MPC823 bus to make this feasi- ble?
FF000000 – FF003FFF MPC823 (on-chip) memory and device registers
F0008000 – FEFFFFFF (not used)
F0000000 – F0007FFF Board device registers
00400000 – EFFFFFFF (not used)
00000000 – 003FFFFF Main memory (DRAM)
Table 2: MPC823FADS Address Map
Address Range Contents
I/O Control Table 3
Indicate which control signals should be activated for each action listed in column 1. Use the letter ‘
E
’ to indicate Enable. Assume empty cells indi-
cate the corresponding control signal is not enabled. MW B0 EN means Memory Write Byte 0 Enable, etc. Assume the memory write enable signalsenables a Clock Enable or Memory Write Enable signal. MR B0 EN means Memory Read Byte 0 enable.Assume the memory read enable signalsenables a tristate enable for the respective byte wide data path.Assume that BAR and 7Segment Led registers are enabled by LEDs Register Enable.
Enable Control
Action
MWB0EN
MWB1EN
MWB2EN
MWB3EN
MRB0EN
MRB1EN
MRB2EN
MRB3EN
Switches-TriStateEnable
LEDs Regis-ter Enable(CE)
PDOUT_EN
Memory Write Byte 0Memory Write Byte 1Memory Write Byte 2Memory Write Byte 3Memory Write 1/2 Word B0-B1Memory Write 1/2 Word B2-B3Memory Write WordMemory Read Byte 0Memory Read 1/2 Word B0-B1Memory Read WordMemory Read Byte 3Switches ReadLEDs Write
