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CS 141 Chien: Caches, Virtual Memory and Cache Replacement Algorithms, Study notes of Computer Architecture and Organization

University of California - San DiegoComputer Architecture and Organization

A collection of notes from a cs 141 lecture by professor chien. The notes cover the topic of caches, virtual memory, and cache replacement algorithms. Information on cache organization, dealing with stores, three types of cache misses, cache replacement, writing cache data back, replacement algorithms, instruction and data caches, caches in current processors, multiple caches and consistency, and virtual memory. The professor also discusses the differences between virtual memory and memory caches, and the use of translation lookaside buffers (tlbs) to make address translation fast.

Typology: Study notes

Pre 2010

Uploaded on 03/28/2010

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koofers-user-gi5 🇺🇸

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CS 141 Chien 1 March 9, 2000
Caches continued and Virtual
Memory
Last Time
–Cache organization
–Dealing with Stores
Today
–Quiz
–Cache entry replacement
–Virtual Memory
Reminders/Announcements
–HW#5 due Tuesday, 3/14, beginning of class
–Final exam, Monday 3/20, 3-6pm, Peterson 110
CS 141 Chien 2 March 9, 2000
Three types of cache misses
Compulsory (or cold-start) misses
–first access to the data.
Capacity misses
–we missed only because the cache isn’t big enough.
Conflict misses
–we missed because the data maps to the same line as other data that forced it
out of the cache.
tag data
address string:
4 00000100
8 00001000
12 00001100
4 00000100
8 00001000
20 00010100
4 00000100
8 00001000
20 00010100
24 00011000
12 00001100
8 00001000
4 00000100
DM cache
pf3
pf4
pf5
pf8
pf9
pfa

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Download CS 141 Chien: Caches, Virtual Memory and Cache Replacement Algorithms and more Study notes Computer Architecture and Organization in PDF only on Docsity!

CS 141 Chien 1 March 9, 2000

Caches continued and Virtual

Memory

 Last Time

  • Cache organization
  • Dealing with Stores

 Today

  • Quiz
  • Cache entry replacement
  • Virtual Memory

 Reminders/Announcements

  • HW#5 due Tuesday, 3/14, beginning of class
  • Final exam, Monday 3/20, 3-6pm, Peterson 110

Three types of cache misses

 Compulsory (or cold-start) misses

  • first access to the data.

 Capacity misses

  • we missed only because the cache isn’t big enough.

 Conflict misses

  • we missed because the data maps to the same line as other data that forced it out of the cache.

tag data

address string: 4 00000100 8 00001000 12 00001100 4 00000100 8 00001000 20 00010100 4 00000100 8 00001000 20 00010100 24 00011000 12 00001100 8 00001000

DM cache

CS 141 Chien 3 March 9, 2000

So, then, how do we decrease...

 Compulsory misses?

 Capacity misses?

 Conflict misses?

Replacement

 What happens to the data in the cache, when we

bring data in?

 Direct Mapped caches

  • No choice which data to replace
  • Only one place to put the incoming data
  • Write the data back to the memory

 Associative Caches

  • Several possible places for the data
  • Choosing which to replace => Replacement policy
  • FIFO, Random, Least Recently Used: don’t matter much for small degrees of associativity

 Writing the data back to the memory

CS 141 Chien 7 March 9, 2000

Instruction and Data Caches

 Caches necessary to support pipelined instruction

execution at high speeds (600 - 1000 Mhz)

 MIPS instruction set has 1-2 memory references

per instruction x Superscalar!

 => Need two caches, one for instructions and one

for data to keep up

P

Instruction Cache

Data Cache

Main Memory

Caches in Current Processors

 Often DM at highest level (closest to CPU), associative

further away

 split I and D close to the processor, unified further

away (for throughput rather than miss rate).

 write-through and write-back both common, but never

write-through all the way to memory.

 32-byte cache lines very common

 Non-blocking

  • processor doesn’t stall on a miss, but only on the use of a miss (if even then)
  • this means the cache must be able to handle multiple outstanding accesses.

CS 141 Chien 9 March 9, 2000

Multiple Caches and Consistency?

 Instruction cache supports Instruction Fetch

 Data cache supports Load/Store operations

 Do they ever share data?

  • Self-modifying code
  • Compiler produces code and links it dynamically

 Hardware must support consistency.

  • Flush Instruction Cache when necessary (delete contents)

 Cache Consistency in Multiprocessors is an

important topic.

Virtual Memory

CS 141 Chien 13 March 9, 2000

Virtual Memory

 What happens if another program in the processor uses

the same addresses that yours does?

 What happens if your program uses addresses that

don’t exist in the machine?

 What happens to “holes” in the address space your

program uses?

 So, virtual memory provides

  • performance (through the cacheing effect)
  • protection
  • ease of programming/compilation
  • efficient use of memory

Virtual Memory

 is just a mapping function from virtual memory

addresses to physical memory locations, which allows

cacheing of virtual pages in physical memory.

CS 141 Chien 15 March 9, 2000

What makes VM different than

memory caches

 MUCH higher miss penalty (millions of cycles)!

 Therefore

  • large pages [equivalent of cache line] (4 KB to MBs)
  • associative mapping of pages (typically fully associative)
  • software handling of misses (but not hits!!)
  • write-through not an option, only write-back

 Generally a functionality enhancement (programs

run), not a performance enhancement (NOT

illusion of a large memory).

Virtual Memory mapping

physical addresses

virtual addresses

virtual addresses

disk

CS 141 Chien 19 March 9, 2000

TLBs and caches

Virtual Memory Summary

 Caches: Location, Organization (block size and

associativity), Replacement

 Virtual memory provides

  • protection, sharing, illusion of large main memory

 Virtual Memory requires twice as many memory

accesses, so we cache page table entries in the

TLB.

 Three things can go wrong on a memory access:

cache miss, TLB miss, page fault.