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Study Material. This lab module will help you become familiar with the TI DSP/BIOS CLK module and system clock. CLK Lab, Connexions Web site. http://cnx.org/content/m36664/1.1/, Jan 7, 2011. David, Waldo, Lab, Module, Prerequisites, Reading, Laboratory, Scheduling, Insert TSK, Code, composer, Task, Function, Test, Clock, Simulator.
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Connexions module: m36664 1
This work is produced by The Connexions Project and licensed under the Creative Commons Attribution License †
Abstract This module is the lab work for the CLK module.
This lab module will help you become familiar with the TI DSP/BIOS CLK module and system clock.
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DSP/BIOS provides two methods of tracking time, the high and low resolution clock managed by the CLK module and the system clock. In this lab the default conguration for the CLK module and system clock will be used. In this case the system clock and the low resolution clock will be the same. In this section you are going to nd the number of counts per millisecond for the CLK module. You will also measure how long it takes a loop in your program to loop 100 times. Then you will measure how long it takes a loop in your program to loop 1000 times. This description assumes you are using CCS v4 or higher and a simulator for the hardware. The simulator is the C6713 Device Cycle Accurate Simulator.
http://cnx.org/content/m36664/1.1/
Connexions module: m36664 2
#include #include #include
main() { }
testClock() { /* your code here */ }
http://cnx.org/content/m36664/1.1/