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CMOS Logic
Bill Wilson
This work is produced by The Connexions Project and licensed under the Creative Commons Attribution License †
Abstract Introducing technology CMOS, that means complementary MOS, including how to make p-channel transistor and how this one works. Consider the following, shown in Figure 1.
Figure 1: A PMOS transistor
This looks a lot like our previous MOSFET except that now we have an n-type substrate and the source and drain regions are p-type. If we apply a negativeVgs (with the source connected to the n-type substrate) then the induced negative charge on the gate will drive away the electrons, and if the bands under the gate are bent up su ciently, form an inversion layer (Figure 2) of holes thus making an enhancement mode p-channel MOSFET, or a PMOS transistor. (As opposed to an NMOS transistor which we studied rst.). Note that a PMOS transistor will have a negative VT. That is, the gate voltage has to be less than the source/substrate voltage in order to turn the device on. The more negative Vgs, the more current we will have owing through the device.
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Figure 2: Inversion of an n-type layer
It turns out that a combination of both an n-channel and a p-channel device on the same circuit can be very advantageous. Such technology is called CMOS, for "complementary MOS". Here is how we use a p-channel transistor in the inverter circuit. First of all, however, we have to see how we would make one. There is a fundamental problem in trying to use both n-channel and p-channel devices in the same circuit. What is it? It would seem we need two dierent kinds of substrates, both a p-type substrate for the n-channel transistor, and an n-type substrate for the p-channel device. There is a way around this problem by making what is called a tank or a moat. A moat is a relatively deep region of one type of material placed into a host substrate of the opposite type (Figure 3). We can put n-type source/drain regions into the p-substrate and p-type source/drain regions into the n-moat. In Figure 4, we will also show the gates, and how the whole inverter is connected together.
Figure 3: Preparing for a CMOS inverter
Vdd and so is the moat! Hence the upper transistor will be turned o. The output will thus be low. If the input voltage is at or near ground (a "low") then the n-channel device is turned o. The voltage between the gate and substrate of the p-channel device is now h −Vdd. (The gate is h 0 and the substrate is at +Vdd.) If the PMOS transistor has a threshold voltage VT of, say, -2 V, then it will be turned on and the output will be high. Note however, that in either state, high or low, there is no static current owing through the inverter. The transfer characteristics for this circuit. Are a little more complicated. First, let's make sure we have our voltages and currents de ned (Figure 6). From the gure, Vgs−n the n-channel gate-source voltage is just Vin. Vgs−p the gate-source voltage for the p-channel device is Vin − VddId−n = Id−p = IdVds−p the drain source voltage for the p-channel transistor can be written as Vds−n − Vdd. We have two sets of characteristic curves (Figure 7): Note that since Vgs−p = Vin − Vdd, when Vin = 0V, Vgs−p = − 5 V and so the transistor is strongly turned on.
Figure 6: De ning voltages
Figure 7: Drain currents for the two transistor as a function of input voltage and Vds
We have a number of dierent "load lines" in this case, because for each Vin we have a dierent curve for both the n and p channel transistors. This is shown in Figure 8. The black spots show the point of intersection. Follow a few of the curves along to see if you agree with where the spots have been placed. We have also added a pair of dotted curves for Vin = 2. 5 V so we can get the "turn-over" point. Projecting the location of the black dots to the Vds−n (or Vout) axis will gives us a value for Vout for each of the input voltages, Vin. The resulting curve is shown in Figure 9. This gives us a good "feel" for how the inverter works, and how the output varies with the input. Note that this transfer curve is quite symmetric about 2. volts, and goes all the way from +5 to 0 volts on the output.
Figure 8: Getting the transfer function
