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¡ Semiconductor MSM82C55A-2RS/GS/VJS
GENERAL DESCRIPTION
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high
speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best
fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU.
This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are
TTL interface compatible.
FEATURES
- High speed and low power consumption due to 3m silicon gate CMOS technology
- 3 V to 6 V single power supply
- Full static operation
- Programmable 24-bit I/O ports
- Bidirectional bus operation (Port A)
- Bit set/reset function (Port C)
- TTL compatible
- Compatible with 8255A-
- 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)
- 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)
- 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)
¡ Semiconductor
MSM82C55A-2RS/GS/VJS
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
E2O0020-27-X
This version: Jan. 1998
Previous version: Aug. 1996
CIRCUIT CONFIGURATION
Group B Port C (Low Order 4 Bits)
Group A Port C (High Order 4 Bits)
Group A Port A (8)
Group B Port B (8)
Group A Control
Group B Control
Data Bus Buffer
Read/ Write Control Logic
VCC
GND
D 0 - D 7
RD
WR
RESET
CS
A 0
A 1
PA 0 - PA 7
PC 4 - PC 7
PC 0 - PC 3
PB 0 - PB 7
Internal Bus Line
ABSOLUTE MAXIMUM RATINGS
–55 to +
MSM82C55A-2RS Supply Voltage V (^) CC –0.5 to +7 V Input Voltage (^) VIN –0.5 to V (^) CC +0.5 V Output Voltage VOUT –0.5 to V (^) CC +0.5 V Storage Temperature T^ STG °C Power Dissipation PD 0.7 W
Parameter Symbol Unit
Ta = 25°C
Conditions Rating MSM82C55A-2GS MSM82C55A-2vJS
Ta = 25°C with respect to GND
OPERATING RANGE
Supply Voltage V (^) CC V T (^) op
Range 3 to 6 –40 to 85
Parameter Symbol Unit
Operating Temperature °C
RECOMMENDED OPERATING RANGE
DC CHARACTERISTICS
Typ. Supply Voltage VCC 5 V Top + "L" Input Voltage VIL — "H" Input Voltage VIH —
Min.
–0.
Max.
+0. V (^) CC + 0.
Parameter Symbol Unit
°C V V
Operating Temperature
Typ. Max. "L" Output Voltage VOL 0.4 V "H" Output Voltage VOH —^ V — V
Parameter Symbol (^) Min. Unit —
IOL = 2.5 mA I (^) OH = –40 mA I (^) OH = –2.5 mA
Conditions
VCC = 4.5 V to 5.5 V Ta = –40°C to +85°C (C (^) L = 0 pF)
Input Leak Current I^ LI 1 mA Output Leak Current ILO 10 mA
0 £ VIN £ VCC
0 £ VOUT £ VCC
CS ≥ VCC –0.2 V
VIH ≥ VCC –0.2 V
VIL £ 0.2 V
Supply Current (Standby) I^ CCS^ mA
8 mA
I/O Wire Cycle 82C55A- ...8 MHzCPU Timing
ICC
Average Supply Current (Active)
MSM82C55A-
AC CHARACTERISTICS
Min. Max. Setup Time of Address to the Falling Edge of RD (^) tAR 20 — ns Hold Time of Address to the Rising Edge of RD tRA 0 — ns
Parameter Symbol Unit Remarks
Setup Time of Address before the Falling Edge of WR t (^) AW 0 — ns
Load 150 pF
(V (^) CC = 4.5 V to 5.5 V, Ta = –40 to +85°C) MSM82C55A-
Delay Time from the Falling Edge of RD to the Output of Defined Data t (^) RD — 120 ns Delay Time from the Rising Edge of RD to the Floating of Data Bus t (^) DF 10 75 ns Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR t (^) RV 200 —^ ns
RD Pulse Width t (^) RR 100 — ns
Hold Time of Address after the Rising Edge of WR t (^) WA 20 — ns WR Pulse Width t (^) WW 150 — ns Setup Time of Bus Data before the Rising Edge of WR t (^) DW 50 — ns Hold Time of Bus Data after the Rising Edge of WR t (^) WD 30 — ns Delay Time from the rising Edge of WR to the Output of Defined Data t (^) WB — 200 ns Setup Time of Port Data before the Falling Edge of RD t (^) IR 20 — ns Hold Time of Port Data after the Rising Edge of RD t (^) HR 10 — ns ACK Pulse Width t (^) AK 100 — ns STB Pulse Width t (^) ST 100 — ns Setup Time of Port Data before the rising Edge of STB t (^) PS 20 — ns Hold Time of Port Bus Data after the rising Edge of STB t (^) PH 50 — ns Delay Time from the Falling Edge of ACK to the Output of Defined Data t (^) AD —^150 ns Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) t (^) KD 20 250 ns Delay Time from the Rising Edge of WR to the Falling Edge of OBF t (^) WOB —^150 ns Delay Time from the Falling Edge of ACK to the Rising Edge of OBF t (^) AOB —^150 ns Delay Time from the Falling Edge of STB to the Rising Edge of IBF t (^) SIB —^150 ns Delay Time from the Rising Edge of RD to the Falling Edge of IBF t (^) RIB —^150 ns Delay Time from the the Falling Edge of RD to the Falling Edge of INTR t (^) RIT —^200 ns Delay Time from the Rising Edge of STB to the Rising Edge of INTR t (^) SIT —^150 ns Delay Time from the Rising Edge of ACK to the Rising Edge of INTR t (^) AIT —^150 ns Delay Time from the Falling Edge of WR to the Falling Edge of INTR t (^) WIT —^250 ns
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
Strobe Output Operation (Mode 1)
WR
INTR
Port Output
tWIT
OBF
t (^) WOB
tWB
tAK tAIT
tAOB
ACK
Bidirectional Bus Operation (Mode 2)
t (^) WOB
t (^) ST
t (^) SIB
t (^) PS t (^) AD t (^) KD
t (^) PH t (^) RIB
t (^) AOB
t (^) AK
WR
INTR
Port A
OBF
ACK
RD
IBF
STB
OUTPUT CHARACTERISTICS (REFERENCE VALUE)
1 Output "H" Voltage (VOH ) vs. Output Current (IOH )
Output Current IOH (mA)
Output "H" Voltage V
OH
(V)
VCC = 5.0 V
Ta = –40 to + 85°C
Output Current IOL (mA)
Output "L" Voltage V
OL
(V)
VCC = 5.0 V
Ta = –40 to +85°C
2 Output "L" Voltage (VOL ) vs. Output Current (I OL )
Note: The direction of flowing into the device is taken as positive for the output current.
BASIC FUNCTIONAL DESCRIPTION
Group A and Group B
When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each.
Group A: Port A (8 bits) and high order 4 bits of port C (PC 7 ~PC 4 )
Group B: Port B (8 bits) and low order 4 bits of port C (PC 3 ~PC 0 )
Mode 0, 1, 2
There are 3 types of modes to be set by grouping as follows:
Mode 0: Basic input operation/output operation (Available for both groups A and B)
Mode 1: Strobe input operation/output operation (Available for both groups A and B)
Mode 2: Bidirectional bus operation (Available for group A only)
When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal
for operation ports (port A for group A and port B for group B) of their respective groups.
Port A, B, C
The internal structure of 3 ports is as follows:
Port A: One 8-bit data output latch/buffer and one 8-bit data input latch
Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer
Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input)
Single bit set/reset function for port C
When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to
turn to low level) any one of 8 bits individually without affecting other bits.
OPERATIONAL DESCRIPTION
Control Logic
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table
below:
Setting of Control Word
The control register is composed of 7-bit latch circuit and 1-bit flag as shown below.
D 0
Definition of input/ output of low order 4 bits of port C.
0 = Output 1 = Input Definition of input/ output of 8 bits of port B.
0 = Output 1 = Input
Mode definition of group B.
0 = Mode 0 1 = Mode 1 Definition of input/ output of high order 4 bits of port C.
0 = Output 1 = Input Definition of input/ output of 8 bits of port A.
0 = Output 1 = Input
Mode definition of group A.
D 7 D 6 D 5 D 4 D 3 D 2 D 1
D 6 D 5 Mode 0 0 Mode 0 0 1 Mode 1 1 ¥ Mode 2
Control word Identification flag
When set to 0, it becomes the control word for bit set/ reset.
Group A Control Bits Group B Control Bits
Be sure to set 1 for the control word to define a mode and input/output.
CS
Input
0 0 Port A Æ Data Bus
Control 1 0 Others 1 0
A 0
WR
Operaiton A 1 Operation
Output
RD
Port B Æ Data Bus Port C Æ Data Bus Data Bus Æ Port A Data Bus Æ Port B Data Bus Æ Port C Data Bus Æ Control Register Illegal Condition Data bus is in the high impedance status.
D 7
Type
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Output
Output
Port A
Output Output
Output
Output
Output Output
Input
Input
Input Input
Input
Input
Input Input
Output
Output
High Order 4 Bits of Port C
Output Output
Input
Input
Input Input
Output
Output
Output Output
Input
Input
Input Input
Output
Output
Port B
Input Input
Output
Output
Input Input
Output
Output
Input Input
Output
Output
Input Input
Input
Output
Control Word Group A Group B Low Order 4 Bits of Port C
Output Input
Input
Output
Ouput Input
Input
Output
Output Input
Input
Output
Output Input
Notes: When used in mode 0 for both groups A and B
2. Mode 1 (Strobe input/output operation)
In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB (Strobe input)
When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)
This is the response signal for the STB. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of STB
and to low level at the rising edge of RD.
INTR (Interrupt request output)
This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge
of the RD when the INTE is set.
INTE A of group A is set when the bit for PC 4 is set, while INTE B of group B is set when the
bit for PC 2 is set.
Following is a description of the output operation of mode 1.
OBF (Output buffer full flag output)
This signal when turned to low level indicates that data is written to the specified port upon
receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of
the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)
This signal when turned to low level indicates that the terminal has received data.
INTR (Interrupt request output)
This is the signal used to interrupt the CPU when a terminal receives data from the CPU via
the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the
internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK
(OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set.
INTE A of group A is set when the bit for PC 6 is set, while INTE B of group B is set when the
bit for PC 2 is set.
Mode 1 Input
(Group A) PA (^7) PA (^0)
INTE A
PC 4
PC 5
STBA
IBF A
PC 3 INTR A
RD
(Group B) PB 7 PB 0
INTE B
PC 2
PC 1
STBB
IBF B
PC 0 INTR B
RD
Note: Although belonging to group B, PC 3 operates as the control signal of group A functionally.
Mode 1 Output
(Group A) PA 7 PA 0
INTEA
PC 7
PC 6
OBFA
ACKA
PC 3 INTRA
WR
(Group B) PB 7 PB 0
INTEB
PC 1
PC 2
OBFB
ACKB
PC 0 INTRB
WR
(b) When group A is mode 1 input and group B is mode 1 output.
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
Selection of I/O of PC 6 and PC 7 when not defined as a control pin.
STBA
IBFA
INTRA
I/O
PC 4
PC 5
PC 3
PC 6, PC 7
PA 7 - PA 0
Group A: Mode 1 Input Group B: Mode 1 Output OBFB ACKB INTRB
PC 1
PC 2
PC 0
PB 7 - PB 0 8
RD
2
1 = Input 0 = Output 8
8
2
WR
3. Mode 2 (Strobe bidirectional bus I/O operation)
In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This
operation is akin to a combination between input and output operations. Port C waits for
the control signal in this case, too. Mode 2 is available only for group A, however.
Next, a description is made on mode 2.
OBF (Output buffer full flag output)
This signal when turned to low level indicates that data has been written to the internal
output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the
high impedance status and the data is not yet output to the outside. This signal turns to low
level at the rising edge of the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)
When a low level signal is input to this pin, the high impedance status of port A is cleared,
the buffer is enabled, and the data written to the internal output latch is output to port A.
When the input returns to high level, port A is made into the high impedance status.
STB (Strobe input)
When this signal turns to low level, the data output to the port from the pin is fetched into
the internal input latch. The data is output to the data bus upon receipt of the RD signal from
the CPU, but it remains in the high impedance status until then.
IBF (Input buffer full flag output)
This signal when turned to high level indicates that data from the pin has been fetched into
the input latch. This signal turns to high level at the falling edge of the STB and low level
at the rising edge of the RD.
INTR (Interrupt request output)
This signal is used to interrupt the CPU and its operation in the same as in mode 1. There
are two INTE flip-flops internally available for input and output to select either interrupt
of input or output operation. The INTE1 is used to control the interrupt request for output
operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt
request for the input operation and it can be set by the bit set for PC4.
Mode 2 I/O Operation
Following is an example of the relation between the control word and the pin when used in
mode 2.
When input in mode 2 for group A and in mode 1 for group B.
PA 7
PA 0
8
INTE 1
PC 7
PC
OBFA
ACKA
RD
PC 3 INTRA
PC 4
PC 5
STBA
IBFA
INTE 2
WR
Port C Function Allocation in Mode 2
PC 0
PC 2
PC 3
PC 1
Port C
Confirmed to the Group B Mode
PC 4
PC 6
PC 7
PC 5
INTRA
STBA
IBFA
ACKA
OBFA
Function
4. When Group A is Different in Mode from Group B
Group A and group B can be used by setting them in different modes each other at the same
time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined
as a control pin in port C to both input and output as port which operates in mode 0 at the
3rd and 0th bits of the control word.
(Mode combinations that define no control bit at port C)
When the I/O bit is set to input in this case, it is possible to access data by the normal port
C read operation.
When set to output, PC 7 -PC 4 bits can be accessed by the bit set/reset function only.
Meanwhile, 3 bits from PC 2 to PC 0 can be accessed by normal write operation.
The bit set/reset function can be used for all of PC 3 -PC 0 bits. Note that the status of port C
varies according to the combination of modes like this.
Group A Group B Port C PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC (^1) 1 2 3 4 5 6 7 8 9 Mode 1 input Mode 0 Output
Mode 0
Mode 0
Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2
Mode 0
Mode 0
Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0
I/O I/O IBFA STBA INTRA I/O^ I/O
PC 0
I/O
OBFA ACKA I/O I/O^ INTRA I/O^ I/O I/O
I/O I/O I/O I/O^ I/O^ STBB IBFB INTRB
I/O I/O I/O I/O I/O ACKB OBFB INTRB
I/O I/O IBFA STBA INTRA STBB IBFB INTRB
I/O I/O IBFA STBA INTRA ACKB OBFB INTRB
OBFA ACKA I/O I/O INTRA STBB IBFB INTRB
OBFA ACKA I/O I/O^ INTRA ACKB OBFB INTRB
OBFA ACKA IBFA STBA INTRA I/O^ I/O I/O
Controlled at the 3rd bit (D3) of the Control Word
Controlled at the 0th bit (D0) of the Control Word
6. Reset of MSM82C55A-
Be sure to keep the RESET signal at power ON in the high level at least for 50 ms.
Subsequently, it becomes the input mode at a high level pulse above 500 ns.
Note: Comparison of MSM82C55A-5 and MSM82C55A-
5. Port C Status Read
When port C is used for the control signal, that is, in either mode 1 or mode 2, each control
signal and bus status signal can be read out by reading the content of port C.
The status read out is as follows:
Group A Group B Status Read on the Data Bus D 7 D 6 D 5 D 4 D^3 D 2 D 1 1 2 3 4 5 6 7 8 9 Mode 1 Input Mode 1 Output Mode 0
Mode 0
Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2
Mode 0
Mode 0
Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0
I/O I/O IBFA INTEA INTRA I/O I/O
D 0
I/O
OBFA INTEA I/O I/O INTRA I/O I/O I/O
I/O I/O I/O I/O I/O INTEB IBFB INTRB
I/O I/O I/O I/O^ I/O^ INTEB OBFB INTRB
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
I/O I/O IBFA INTEA INTRA INTEB OBFB INTRB
OBFA INTEA I/O I/O^ INTRA INTEB IBFB INTRB
OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
OBFA INTE 1 IBFA INTE 2 INTRA I/O I/O I/O
Mode 2
Mode 2
Mode 1 Input Mode 1 Output
OBFA INTE 1 IBFA INTE 2 INTRA INTEB IBFB INTRB
OBFA INTE 1 IBFA INTE 2 INTRA INTEB OBFB INTRB
MSM82C55A-
After a write command is executed to the command register, the internal latch is cleared in
PORTA PORTC. For instance, 00H is output at the beginning of a write command when
the output port is assigned. However, if PORTB is not cleared at this time, PORTB is
unstable. In other words, PORTB only outputs ineffective data (unstable value according
to the device) during the period from after a write command is executed till the first data
is written to PORTB.
MSM82C55A-
After a write command is executed to the command register, the internal latch is cleared in
All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command
when the output port is assigned.
