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Main points of this exam paper are: Column Offset, Dram Chip, Decimal, Memory System, Indicate Bit Width, Datapath, Immediate Value, Shift Amount, Shift Type, Arithmetic
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4 problems, 6 pages Exam Three 12 April 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 total 30 26 26 18 100
4 problems, 6 pages Exam Three 12 April 2012 Problem 1 (3 parts, 30 points) Memory Systems Part A (12 points) Consider a 1 Gbit DRAM chip organized as 32 million addresses of 32 -bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two). total number of bits in address number of columns column decoder required ( n to m ) number of words per column type of mux required ( n to m ) number of address lines in column offset Part B (10 points) Consider an 8 Gbyte memory system with 1 billion addresses of 64 -bit words using a 32 million address by 32-bit word memory DRAM chip. word address lines for memory system chips needed in one bank banks for memory system memory decoder required ( n to m ) DRAM chips required Part C (8 points) Design a 16 million address by 4 bit memory system with 4 million x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if necessary. Be sure to include the address bus, data bus, and MSEL.
4 problems, 6 pages Exam Three 12 April 2012 Problem 3 (3 parts, 26 points) Microcode Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values, except memory addresses, in hexadecimal notation. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field. In each part, modify only registers 7 & 8. Part A (5 points) R 7 =(^ R 8 −^12 )/^128 # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 Part B (15 points) Compute the logical OR of mem[4000] and R 3 and store the result in mem[4004] (that is, mem[4004] gets mem[4000]+R 3 , where “+” is “logical or”). # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 4 5 6 Part C (6 points) R 7 =^15 ⋅ R 8 (multiply R 8 by 15) # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 4
4 problems, 6 pages Exam Three 12 April 2012 Problem 4 (2 parts, 18 points) Counters Part A (8 points) Design a toggle cell using only transparent latches and basic gates (XOR, AND, OR, NAND, NOR, NOT). Use an icon for the transparent latches. Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR , clock inputs Φ 1 and Φ 2 , and an output Out. The CLR^ signal has precedence over TE. Label all signals. Also complete the behavior table for the toggle cell. TE CLR CLK Out 0 0 ↑↓ 1 0 ↑↓ 0 1 ↑↓ 1 1 ↑↓ Part B (10 points) Now combine these toggle cells to build a divide by thirteen counter. Your counter should have an external clear, external count enable, and four count outputs O 3 , O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, XOR & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design must support multi-digit systems. TE CLR Out TE CLR Out TE CLR Out TE CLR Out
