Column Number - Computer Engineering - Exam, Exams of Computer Science

Main points of this exam paper are: Column Number, Maximum Credit, Computer Engineering, Gbit Dram Chip, Decoder Required, Mux Required, Muxes Required, Column Number, Column Offset, Decoder Required

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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ECE 2030 11:00am Computer Engineering Fall 2003
4 problems, 5 pages Exam Three 19 November 2003
1
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have
a question, raise your hand and I will come to you. Please work the exam in pencil and do not
separate the pages of the exam. For maximum credit, show your work.
Good Luck!
Your Name (please print) ________________________________________________
1 2 3 4 total
12 32 21 35 100
pf3
pf4
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4 problems, 5 pages Exam Three 19 November 2003

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!

Your Name ( please print ) ________________________________________________

1 2 3 4 total

4 problems, 5 pages Exam Three 19 November 2003

Problem 1 (3 part, 12 points) Instruction Formats

An instruction format has the following field lengths for R-type and I-type instructions. Answer the following questions:

opcode RD RS1 RS 12 bits 9 bits 9 bits 9 bits opcode RD RS1 immediate value 12 bits 9 bits 9 bits 28 bits

Part A (4 points) How many registers are there?

Part B (4 points) How many instruction types are there?

Part C (4 points) What is the range of immediate values?

Problem 2 (3 parts, 32 points) Memory Systems

Part A (12 points) Consider a 4 Gbit DRAM chip organized as 512 million addresses of 8 bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal.

number of columns column decoder required ( n to m )

type of mux required ( n to m ) number of muxes required number of address lines in column number

number of address lines in column offset

Part B (10 points) Consider a 256 Mbyte memory system with 64 million addresses of 4 byte words using 16 Mbit DRAM chips organized as 4 million addresses by 4 bit words.

word address lines for memory system

chips needed in one bank banks for memory system

memory decoder required ( n to m ) DRAM chips required

4 problems, 5 pages Exam Three 19 November 2003

Problem 4 (6 parts, 35 points) Microcode Reverse Engineering

The microcode fragment below is a mysterious program that runs on the provided datapath handout. All values are in hexadecimal. Unfortunately, don’t care values (X) have been converted to zeros. For full credit, be as specific and concise as you can (e.g., list shift types, amounts, and directions, logical functions, memory addresses and operations, etc.)

cycle X Y Z rwe im en im va au en -a/s lu en lf su en st ld en st en r/-w msel 1 0 0 1 1 1 3E8 0 0 1 C 0 0 0 0 0 0 2 1 0 2 1 0 0 0 0 0 0 0 0 1 0 1 1 3 2 0 3 1 1 10 0 0 0 0 1 0 0 0 0 0 4 2 0 2 1 1 FFFF^0 0 1 8 0 0 0 0 0 5 3 2 2 1 0 0 1 0 0 0 0 0 0 0 0 0 6 2 0 2 1 1 1 0 0 0 0 1 1 0 0 0 0 7 1 2 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Part A (5 points) Describe the operation that occurs during cycle 2 (be specific)?

For the remaining parts, assume R2 contains the value 0x80100204 (hexadecimal) following cycle 2. Part B (5 points) What is the value (in hexadecimal) in R3 when cycle 3 completes?

Part C (5 points) What is the value (in hexadecimal) in R2 when cycle 4 completes?

Part D (5 points) What is the value (in hexadecimal) in R2 when cycle 6 completes?

Part E (5 points) Describe the operation that occurs during cycle 7 (be specific).

Part F (10 points) Describe the operation of this microcode fragment (be specific).

memory

register

file

32 x 32

5

5

5

rwe

X

Y

Z au en

-a/s

arithmetic

unit

sign extender

im va

im en

lu en

logical

unit

lf 4

addr data

r/-w

msel

st en ld en

shift types0 = logical1 = arithmetic2 = rotate+ count shifts right- count shifts left

logical functionsX

Y

out

lf

0

lf

1

lf

2

lf

3

cycle

cycle number

X^

register driven onto X bus

Y^

register driven onto Y bus

Z^

register written from Z bus

rwe

register write enable

im en

immediate enable on Y bus

im va

immediate value

au en

arithmetic unit enable

-a/s

-add / sub (0 = add, 1 = subtract)

lu en

logical unit enable

lf^

logical function

su en

shift unit enable

st^

shift type

ld en

load enable

st en

store enable

r/-w

read/-write (0 = write, 1 = read)

msel

memory select

description

operation description

su en

shiftunit

st 2

count

16 32