Combinational Circuits: Multiplexer Fundamentals and Applications, Study notes of Logic

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Combinational Circuits

By : Ali Mustafa

Multiplexer

• Also called Data selector
• A digital circuit which selects one of the n data

inputs and route it to the single output.

• Select lines (n) and Input lines are ( 2 n)

Necessity of Multiplexer

• In most of the digital circuits, data is available

on more than 1 line

• It is essential to route this data over a single

line

• It reduces the number of wires,complexity,cost

Classification of Multiplexer

2:1 multiplexer

4:1 multiplexer

8:1 multiplexer

16:1 multiplexer

4 : 1 Multiplexer

• Data inputs are 4 (I 0 - I 3 )
• Select input are 2 (S1 , S2)

8 : 1 Multiplexer

• Data inputs are 8 (D 0 – D 7 )
• Select input are 3 (S1 , S2 ,S3)
• Make Truth Table
  • S1’S2’S3’D0 - S1S2S3D

MUX Output

D

D

E

S1 S2 S

Cascading of Multiplexers

• Obtain 8:1 MUX using 4:1 MUXES

MUX

Output

D

D

S1 S

MUX

E

D

D

Cascading of Multiplexers

• Obtain 16:1 MUX using 8:1 MUXES
• Obtain 4:1 MUX using 2:1 MUXES

multiplexer demultiplexer 4x4 switch

control (^) control

Making Connections

• Direct point-to-point connections between gates
  • Wires we've seen so far
• Route one of many inputs to a single output --- multiplexer
• Route a single input to one of many outputs --- demultiplexer

NAND Gate Implementation of Muxes

• 2:1 mux
• 4:1 mux

A B C F 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

C'

C'

0

1 A^ B

S1 S

F

0 1 2 3

4:1 MUX

C' C' 0 1

F

A B C

0 1 2 3 4 5 6 7 1 0 1 0 0 0 1 1

S

8:1 MUX

S1 S

Multiplexers as General-purpose Logic

• 2 n-1:1 mux can implement any function of n variables
  • With n-1 variables used as control inputs and
  • Data inputs tied to the last variable or its complement
• Example:
  • F(A,B,C) = m0 + m2 + m6 + m

= A'B'C' + A'BC' + ABC' + ABC

= A'B'(C') + A'B(C') + AB'(0) + AB(1)

Example

• Implement the following expression using 8:

MUX

F (a,b,c) = m (0,2,4,6)

MUX

Logic 1

Logic 0 a b c

Output

Decrementation in MUX

D0 D1 D2 D3 D4 D5 D6 D

a’ 0 1 2 3 4 5 6 7

a 8 9 10 11 12 13 14 15

D0 D1 D2 D

a’ 0 1 2 3

a 4 5 6 7

a’ a 1 0

a’ 1 0 a a’ 0 1 a

8 Inputs reduces to 4. 8:1 – 4:

16 Inputs reduces to 8. 16:1 – 8:

Example

• Implement the logic function using 4:1 MUX

F (a,b,c) = ∑m (1,3,4,6)

8: MUX

0

2

4

6

Logic 0 c b a

Output

Logic 1 D0 D1 D2 D a’ 0 1 2 3 a 4 5 6 7 a a’ a a’

MUX

c b

Output

a (^) a’