Prepare for your exams
Get points
Guidelines and tips
Sell on Docsity
Docsity AI

Prepare for your exams

Study with the several resources on Docsity

Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips

Sell on Docsity

Docsity AI

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents

20 Points

For each uploaded document

Answer questions

5 Points

For each given answer (max 1 per day)

All the ways to get free points

Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

Combinational Implementation Using Decoder, Encoder-Gates, Truth Tables and Digital Logic Design-Lecture Slides, Slides of Digital Logic Design and Programming

Punjab Engineering College Digital Logic Design and Programming

This course includes logic operators, gates, combinational and sequential circuits are studied along with their constituent elements comprising adders, decoders, encoders, multiplexers, as well as latches, flip-flops, counters and registers. This lecture includes: Combinational, Circuit, Implementation, Decoders, Encoders, Priority, Function, Sum, Minterms, Full, Adder, Complements

Typology: Slides

2011/2012

Uploaded on 08/07/2012

anjushree 🇮🇳

4.4

(54)

147 documents

1 / 16

This page cannot be seen from the preview

Don't miss anything!

Overview of Last Lecture

◦ Decoder'

 Where'to'use?'

 Selec0on'of'De‐selec0on'of'one'of'the'devices'

 Types'of'Decoders?'

 Ac0ve'High'Enable,'Ac0ve'High'Output'

 Ac0ve'High'Enable,'Ac0ve'Low'Output'

 Ac0ve'Low'Enable,'Ac0ve'High'Output'

 Ac0ve'Low'Enable,'Ac0ve'Low'Output'

◦ Construc0on'of'large'decoders'with'smaller'

decoders'

docsity.com

Discover Slides of Digital Logic Design and Programming Punjab Engineering College

Partial preview of the text

Download Combinational Implementation Using Decoder, Encoder-Gates, Truth Tables and Digital Logic Design-Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Overview of Last Lecture

◦ Decoder

 Where to use?

 Selec0on of De‐selec0on of one of the devices

 Types of Decoders?

 Ac0ve High Enable, Ac0ve High Output

 Ac0ve High Enable, Ac0ve Low Output

 Ac0ve Low Enable, Ac0ve High Output

 Ac0ve Low Enable, Ac0ve Low Output

◦ Construc0on of large decoders with smaller

decoders

Today’s Lecture

◦ Combina0onal Circuit Implementa0on using

Decoders

◦ Encoder

◦ Priority Encoder

Implementation of Full Adder with a Decoder

 There are three inputs and eight outputs so we

need 3-to-8-line decoder

 Two OR gates are required for logical sum of the

desired minterms

Implementation of Full Adder with a Decoder Contd..  A function with long list of minterms requires an OR gate with large number of inputs  A function having a list of K minterms can be expressed in its complemented form F’ with 2

n

K minterms  If the number of minterms in a function is greater than 2

n

/2 then F’ can be expressed with fewer minterms  In such case it is advantageous to use a NOR gate to sum the minterms of F’. The output of the NOR gate complements this sum and generates the normal output F

Encoder: Example

 An example of encoder is octal-to-binary encoder

 It has eight inputs (one for each octal digits) and

three outputs that generate the corresponding

binary number

 It is assumed that only one input has a value of 1 at

any given time

 The encoder can be implemented with OR gates

whose inputs are determined directly from the truth

table

 Output z is equal to 1 when the input octal digit is

1,3,5 or 7. Output y is 1 for octal digits 2,3,6 or 7

and output x is 1 for digits 4,5,6 or 7. These

conditions can be expressed as by the Boolean

functions as shown in the next slide

Truth Table: Octal to Binary Encoder Outputs Inputs X Y Z D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 z=D 1 +D 3 +D 5 +D 7 y=D 2 +D 3 +D 6 +D 7 x=D 4 +D 5 +D 6 +D 7

Previous Encoder Limitations

 The encoder defined in the last slide has the

limitation that only one input can be active at any

given time. If two inputs are active simultaneously,

the output produces an undefined combination.

 For example

◦ If input D 3 and D 6 are 1 simultaneously the output of the encoder will be 111 (see truth table and Boolean function for outputs). Since z=D 1 +D 3 +D 5 +D 7 y=D 2 +D 3 +D 6 +D 7 x=D 4 +D 5 +D 6 +D 7 ◦ This 111 doesn’t represent either binary 3 or binary 6

 To resolve this ambiguity, encoder circuit must

establish an input priority to ensure that only one

input is encoded.

 Another ambiguity is that when all inputs are zero,

output with all zeros is generated. This is same as

when D

is equal to 1. This discrepancy can be

resolved by providing an output to indicate that at

least one input is equal to 1

Priority Encoder

 A priority encoder is an encoder circuit that

includes the priority function.

 The operation of the priority encoder is such that if

two or more inputs are equal to 1 at the same time,

the input having the highest priority will take

precedence

◦ D 3 has the highest priority ◦ D 0 has the lowest priority

 Valid bit indicator (V) is set to 1 when one or more

inputs are equal to 1. If all inputs are 0, there is no

valid inputs and V is equal to 0. The other two

outputs are not inspected when V equals 0 and are

specified as don’t care conditions

Priority Encoder: Truth Table

Input Output D 0 D 1 D 2 D 3 x y v 0 0 0 0 X X 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1

X: don't-care conditions in the output, used in the inputs to condense truth table, replaced by both 0 and then 1
V: valid output indication, implemented by OR function

Combinational Implementation Using Decoder, Encoder-Gates, Truth Tables and Digital Logic Design-Lecture Slides, Slides of Digital Logic Design and Programming

Related documents

Partial preview of the text

Download Combinational Implementation Using Decoder, Encoder-Gates, Truth Tables and Digital Logic Design-Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Overview of Last Lecture

◦ Decoder

 Where to use?

 Selec0on of De‐selec0on of one of the devices

 Types of Decoders?

 Ac0ve High Enable, Ac0ve High Output

 Ac0ve High Enable, Ac0ve Low Output

 Ac0ve Low Enable, Ac0ve High Output

 Ac0ve Low Enable, Ac0ve Low Output

◦ Construc0on of large decoders with smaller

decoders

Today’s Lecture

◦ Combina0onal Circuit Implementa0on using

Decoders

◦ Encoder

◦ Priority Encoder

 There are three inputs and eight outputs so we

need 3-to-8-line decoder

 Two OR gates are required for logical sum of the

desired minterms

n

n

Encoder: Example

 An example of encoder is octal-to-binary encoder

 It has eight inputs (one for each octal digits) and

three outputs that generate the corresponding

binary number

 It is assumed that only one input has a value of 1 at

any given time

 The encoder can be implemented with OR gates

whose inputs are determined directly from the truth

table

 Output z is equal to 1 when the input octal digit is

1,3,5 or 7. Output y is 1 for octal digits 2,3,6 or 7

and output x is 1 for digits 4,5,6 or 7. These

conditions can be expressed as by the Boolean

functions as shown in the next slide

Previous Encoder Limitations

 The encoder defined in the last slide has the

limitation that only one input can be active at any

given time. If two inputs are active simultaneously,

the output produces an undefined combination.

 For example

 To resolve this ambiguity, encoder circuit must

establish an input priority to ensure that only one

input is encoded.

 Another ambiguity is that when all inputs are zero,

output with all zeros is generated. This is same as

when D

is equal to 1. This discrepancy can be

resolved by providing an output to indicate that at

least one input is equal to 1

Priority Encoder

 A priority encoder is an encoder circuit that

includes the priority function.

 The operation of the priority encoder is such that if

two or more inputs are equal to 1 at the same time,

the input having the highest priority will take

precedence

 Valid bit indicator (V) is set to 1 when one or more

inputs are equal to 1. If all inputs are 0, there is no

valid inputs and V is equal to 0. The other two

outputs are not inspected when V equals 0 and are

specified as don’t care conditions

Priority Encoder: Truth Table

Maps for Priority Encoder

THE END