Decoder, Encoder-Digital Logic Design-Lecture Slides, Slides of Digital Logic Design and Programming

This course includes logic operators, gates, combinational and sequential circuits are studied along with their constituent elements comprising adders, decoders, encoders, multiplexers, as well as latches, flip-flops, counters and registers. This lecture includes: Decoder, Encoder, Combinational, Circuit, Convert, Coded, Information, BCD, 7, segment, Display, Minterms, Octal

Typology: Slides

2011/2012

Uploaded on 08/07/2012

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Overview of Last Lecture
BCD$Adder$
Binary$Mul0plier$
Magnitude$Comparator$
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Download Decoder, Encoder-Digital Logic Design-Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Overview of Last Lecture

– BCD Adder

– Binary Mul0plier

– Magnitude Comparator

Today’s Lecture

  • Decoder
  • Encoder

Decoder Example (Code Converter)

  • BCD-to-seven-segment display converter

3-to-8-Line Decoder

  • A 3-to-8-Line Decoder is a decoder in which three

inputs are decoded into eight outputs, each

representing one of the minterms of the three

input variables

  • Each one of the eight AND gates generates one of

the minterms

  • A particular application of this decoder is binary-

to-octal converion, however 3-to-8-line decoder

can be used for decoding any 3-bit code to

provide eight outputs, one for each element of

the code

3-to-8-Line Decoder Truth Table

Inputs Outputs X Y Z D0 D1 D2 D3 D4 D5 D6 D 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

Decoders with NAND gates

  • Some decoders are constructed with NAND gates.

Since a NAND gate produces the AND operation with

inverted output, it becomes more economical to

generate the decoder minterms in their complemented

form. Decoder include one or more enable inputs to

control the circuit operation

  • A 2-to4-line decoder with an enable input is shown

next. (see fig).

  • The circuit operates with complement outputs and a complement enable input.
  • The decoder is enabled when E is equal to 0 and disabled when E = 1
  • The output whose value is equal to 0 represents the minterm selected by inputs A and B.
  • Only one output can be zero at any given time, all other outputs are 1
  • Some decoders have two or more enable inputs that

must satisfy a given logic condition

Constructing large Decoders

  • Decoders with enable inputs can be connected

together to form a larger decoder circuit.

  • two 3-to-8 decoder can be connected to form a 4-to- decoder
  • The top decoder outputs generates minterms 0000 to 0111 and the bottom decoder outputs generate minterms 1000 to
     Generates from 0000 to 0111 

Generates from 1000 to 1111

THE END