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An overview of compiler optimizations, including function call optimizations, loop optimizations, memory access optimizations, control flow optimizations, data flow optimizations, and machine-specific optimizations. It covers various optimization techniques such as procedure integration, loop unrolling, instruction scheduling, and register allocation.
Typology: Assignments
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^ Compiler optimization is a misnomer. ^ A code-improving transformation consists of asequence of changes that preserves the semanticbehavior (i.e. are safe). ^ A code-improving transformation attempts to makethe program^ ñ^ run faster^ ñ^ take up less space^ ñ^ consume less power ^ An optimization phase consists of a sequence ofcode-improving transformations of the same type.
^ Invariant code motion ^ Strength reduction ^ Induction variable elimination ^ Unrolling ^ Collapsing ^ Fusion ^ Software pipelining
^ Common subexpression elimination ^ Partial redundancy elimination ^ Dead assignment elimination ^ Evaluation order determination ^ Recurrence elimination
^ Accomplished by combining RTLs. ^ Data dependences (links) are detected betweenRTLs. ^ Pairs or triples of RTLs are symbolically merged. ^ Legality is checked via a machine description.
r[1] = r[30]+i; 27 {26}
r[2] = M[r[1]]; r[1]: ^ r[2] = M[r[30]+i]; r[1] = r[30]+i; r[1]:orr[2] = M[r[30]+i];
r[1]:
r[2] = M[r[3]]; 32 {31}
r[2] = r[2]+1; 33 {32}
M[r[3]] = r[2]; r[2]: ^ M[r[3]] = M[r[3]]+1; r[2] = M[r[3]]+1; r[2]:orM[r[3]] = M[r[3]]+1; r[2]:
r[36]=r[5]; 39 {38}
r[36]=r[36]+i; 40
r[37]=r[5]; 41 {40}
r[37]=r[37]+i; 42 {41}
r[40]=M[r[37]];
r[37]:
r[41]=1; 44 {42}
r[42]=r[40];
r[40]:
r[42]=r[42]+r[41];
r[41]:
M[r[36]]=r[42];
r[42]:r[36]:
r[36]=r[5]; 39 {38}
r[36]=r[36]+i; 40
r[37]=r[5]; 42 {40}
r[40]=M[r[37]+i]];
r[37]:
r[41]=1; 44 {42}
r[42]=r[40];
r[40]:
r[42]=r[42]+r[41];
r[41]:
M[r[36]]=r[42];
r[42]:r[36]:
r[36]=r[5]; 39 {38}
r[36]=r[36]+i; 42
r[40]=M[r[5]+i]]; 43
r[41]=1; 44 {42}
r[42]=r[40];
r[40]:
r[42]=r[42]+r[41];
r[41]:
M[r[36]]=r[42];
r[42]:r[36]:
r[36]=r[5]; 39 {38}
r[36]=r[36]+i; 43
r[41]=1; 44
r[42]=M[r[5]+i]]; 45 {43,44}
r[42]=r[42]+r[41];
r[41]:
M[r[36]]=r[42];
r[42]:r[36]:
for (sum=0, j = 0; j < n; j++)sum = sum + a[j]; ^ after instruction selectionM[r[13] + sum] = 0;M[r[13] + j] = 0;PC = L18;L19r[0] = M[r[13] + j] <<2;M[r[13] + sum] = M[r[13] + sum] + M[r[0] + _a];M[r[13] + j] = M[r[13] + j] + 1;L18IC = M[r[13] + j]? M[_n];PC = IC < 0
→L19;
^ after register allocation^ r[2]^ = 0;^ r[1]^ = 0;PC = L18;L19r[0] =
r[1]^ << 2; r[2] =^ r[2]^ + M[r[0] + _a]; r[1] =^ r[1]^ + 1; L18IC =^
r[1]^? M[_n];PC = IC < 0^ →
L19;
^ after code motionr[2] = 0;r[1] = 0;^ r[4] = M[_n];^ PC = L18L19r[0] = r[1] << 2;r[2] = r[2] + M[r[0] + _a];r[1] = r[1] + 1;L18IC = r[1]?
r[4] ; PC = IC < 0
→^ L19;
after loop strength reductionr[2] = 0;r[1] = 0;r[4] = M[_n];^ r[3] = _a;^ PC = L18L19r[2] = r[2] + M[
r[3] ]; r[3] = r[3] + 4; r[1] = r[1] + 1;L18IC = r[1]? r[4];PC = IC < 0
→^ L19;
^ after induction variable eliminationr[2] = 0;r[4] = M[_n] << 2;r[3] = _a;^ r[4] = r[4] + r[3];^ PC = L18;L19r[2] = r[2] + M[r[3]];r[3] = r[3] + 4;L18IC =^
r[3]^?^ r[4]
; PC = IC < 0
→^ L19;
r[1] = M[r[13] + i] << 2;r[1] = M[r[1] + _b];r[2] = M[r[13] + i] << 2;r[2] = M[r[2] + _b]; r[1] = M[r[13] + i] << 2;r[1] = M[r[1] + _b];r[2] = r[1];
PC = L12;r[1] = M[r[13] + i];r[1] = r[5] + r[1];M[r[13] + j] = r[1];L13 PC = L12;L13
IF a THEN b
While c DO d
compiles into
compiles into
a^
L2:^ c
PC = IC != 0
b^
d