EECS 141: SPRING 01 --MIDTERM 2
Prof. Andrei Vladimirescu
The transistors in the following problems are minimum-length (0.25 um) devices fabricated in a 0.25 um process; the only model parameters you need are the zero-bias Vto and back-gate bias modified Vt threshold voltages:
NMOS: Vtno = 0.4 V, Vtn = 0.7 V;
PMOS: Vtpo = -0.4 V, Vtp = -0.7 V.
The supply voltage is Vdd = 2.5 V.
Problem 1. Static CMOS Logic
Consider the two complementary static CMOS gates shown below.
a) Do they implement the same logic function? What logic function(s) do they implement?
b) Considering the transistor sizes shown what is the worst-case input pattern (A-E) from a delay perspective for Circuit A, and, for Circuit B? Explain. Assume that an NMOS transistor has the same ON-resistance as a three times wider PMOS.
EE 141 Midterm#2, Spring 01
EECS 141: SPRING 01 --MIDTERM 2 1
