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EECS 141: Fall 1992 - MIDTERM 2
J.M. Rabaey
For all the problems, you can assume the following transistor parameters:
NMOS: VTn = 0.75V, Kn = 20 uA/V^2 , LAMBDA = 0.05, GAMMA = 0.5 V1/2^ , 2PHIF = -0.6V PMOS: VTp = -0.75V, Kp = 7 uA/V^2 , LAMBDA = 0.1, GAMMA = 0.5 V1/2^ , 2PHIF = -0.6V NPN: BF = 100, VBE(on) = 0.7V, VBE(sat) = 0.8V, VCE(sat) = 0.1V, IS = 10-17A
For all problems, you may assume that the MOS transistor lengths indicated are the effective lengths (Leff) or, equivalently, that LD = 0.
Problem 1: Logic Gates
The circuits shown below have a major problem. For each of those circuits,
a). Determine its logic function. b). Explain the problem. c). Redraw the circuit such that the problem is solved. Try to keep the number of changes minimal (e.g. if a circuit is dynamic, keep it such). Also, stick to the available input signals.
Circuit 1:
a). Logic function:
A B X OUT
OUT = or OUT = (depending on what you want "?" to be)
b). The problem:
Node X is not driven by input when B=0 A=1, so X will keep its previous value. Need to make sure X is driven by one and only one input at all times.
c). Redrawn Circuit:
Circuit 2:
a). Logic Function:
OUT =
b). The problem:
PMOS W/L too large compared to 1/3 NMOS W/L. So VOL will be very high. Want RPMOS >> RNMOS + RNMOSB + RNMOSC --> 1/(up) x 1/(W/L|p) >> 3/(un x W/L|n) un/up ~ 1.8/2.
VM: This is a symmetric differential circuit, so VM = (VOL + VOH) / 2 = -0.1V
VIH, VIL: Remember, this isa differential circuit, so In and In changes. When VIn - VIn = 120mV, IC1 = 100 IC So, VIH = VM + 60mV = -0.09V VIL = VM - 60mV = -0.21V
b). Assume that the output Out connects the input terminal of 5 identical gates (or has a fanout of 5). Recompute the values of VOH and VOL under these conditions.
When an ouput is low base current inot load = 0. So VOL stays at -0.30V.
When output is high, each load draws base current = 400mA/BF = 4mA
So, VOH = 0 - 5 x 4mA x 750Ohm = -0.015V
c). Assume that the capacitance to the outputs of the gate equals 40fF and that there are no other capacitors in the circuit. You can ignore QF. Compute the power consumption of the gate. Assume that the input is high 50% of the time and makes a transition (L -> H or H -> L) every 5 nsec. Assume that the input is high for 50% of the time.
Pstatic = IEE (VCC - VEE) = (400uA)(3V) = 1.2mW
Pdynamic: with each transition, one 40fF capacitor is charged. Energy/Transition = (VCC - VEE)(VOH - VOL) CL = (3V)(0.3V)(40fF) = 36fJ Hence, Pdynamic = 36fJ/5nsec = 7.2uW
Ptotal = Pstatic + Pdynamic ~ Pstatic = 1.2mW
Problem 3: Dynamic CMOS
After taking EE141, a student figured out that dynamic circuits were way too complex and came up with his "new" dynamic style called BDL (for Berkeley Dynamic Logic). A gate in this logic style is shown in the Figure below.
a). Is this circuit going to work under all conditions? If not, explain why and give a case when this circuit is not going to work.
No. If inputs are high during precharge, the output will fail to precharge to VDD. (Why would inputs be high during precharge? Well, if you use "BDL" in domino or np CMOS, that could happen.)
b). Given the set of input waveforms, shown on the next page, draw the voltage waveforms for both the intermediate node X and output Out. Both have an initial value of 0V. Determine the voltage levels precisely and mark them on the drawing. You may assume that all input signals change abruptly. All capacitances have been lumped and their values have been annotated on the Figure above. To compute the transient response, you may assume that all transistors (NMOS and PMOS) can be modeled as linear resistors with a value of 15kOhm. Assume that CGS and CGD = 0 for all transistors.
Vout(2nsec) = 4.
Vout(3nsec) = 4.
Vout(7nsec) = 3.
x Clock Feedthrough Can be Reduced by Reducing the Size of precharge Transistor.
x NAND logic is preferred over NOR logic in dynamic Gates with NMOS PDN.
x Implementing a NAND function is Not possible in DOMINO.
x Dynamic Logic is the Logic Style with the Smallest Number of Transistors
x The Propagation Delay of a Dynamic Gate is Linear with Respect to Fanin.
x Clock FeedThrough Can Hurt the Power Consumption.
Increasing the Fanout of a Dynamic Gate Does Not Affect the Noise Margins.
x Dynamic Logic is Often Used in Portable Cameras for Its Low Power Consumption.
