Computer Achitecture and org- Fixed point Multiplication- Saritha, Study notes of Computer Architecture and Organization

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Binary Multiplication

Some general observations

• (^) Multiplication involves the generation of partial

products – one for each digit in the multiplier.

• (^) Partial products are summed to produce the final

product.

• (^) Partial products are very simple to define for binary

multiplication. If the digit is a ‘one’ the partial product

is the multicand, otherwise the partial product is zero.

• (^) The total product is the sum of the partial products.

Each successive partial product is shifted one position

to the left.

• (^) The multiplication of two n-bit binary numbers results in

a product of up to 2n bits in length.

Simplifying Multiplication

• The processor can keep a running product

rather than summing at the end.

• For each ‘1’ in the multiplier we can apply

an add and a shift.

• For each ‘0’ only a shift is needed.

Hardware Implementation for Signed-Magnitude Multiplication

Flow chart for Multiplication (Signed Magnitude Representation)

Multiply Operation Multiplicand in B Multiplier in Q AS ← QS + BS QS ← QS + BS A ← 0, E ← 0 SC ← n – 1 Qn ≠ 0 = 0 EA ← A + B Shr EAQ SC ← SC – 1 SC END (Product is in AQ) = 0 = 1 E A Q SC 0 00000 10011 101 10111 10111 0 01011 11001 100 10111 00010 0 10001 01100 011 1 0 01000 10110 010 0 00100 01011 001 10111 11011 0 01101 10101 000 Add Add Add Shift Shift Shift Shift Shift 23 × 19 = 437 Q = 19 (10011), B = 23 (10111)

Group Exercise: Group 1: 3 X 7, Group 2: -3 X 7, Group 3: 3 X -7, Group 4: -3 X -

E

Example: 11 × 13

Observation

M X (00011110) = M X (

4

3

2

1

= M X (16 + 8 + 4 + 2)

= M X 30

The number of operations can be reduced to two if we

observe that:

n

n-

n-k

n+

• 2 n-k

M X (00011110) = M X (

5

• 2 1

= M X (32 - 2)

= M X 30

14 = 01110 = 2^4 – 2^1 = 16 – 2 25 = 011001 = - 0

• 2 1

• 2 3 + 2 5 = -1 + 2 – 8 + 32 = 1 – 8 + 32 = -7 + 32

Booth Multiplication Algorithm (2’ complement multiplication) 7 × 3 = 21 0111 multiplicand = 7 × 0011(0) multiplier = 3 11111001 bit-pair 10, add -7 in two’s compl. bit-pair 11, do nothing 000111 bit-pair 01, add 7 bit-pair 00, do nothing 00010101 21

• (^) -7 × 3 = - 1001 multiplicand = -7 in two’s com. ×0011(0) multiplier = 3 00000111 bit-pair 10, add 7 bit-pair 11, do nothing 111001 bit-pair 01, add - bit-pair 00, do nothing 11101011 -

Booth Advantage

× 00011110 30

00000000 ________

× 00011110 30

---

0000001001011000 600 Serial addition Booth algorithm Four partial product additions Two partial product additions

Flowchart for Booth Multiplication Multiply Multiplicand in BR Multiplier in QR AC ← 0 Qn+1 ← 0 SC ← n QnQn+ AC ← AC + BR + 1 AC ← AC + BR ashr (AC & QR) SC ← SC – 1 SC ≠ (^0) = 0 = 10 = 01 = 00 = 11 END Comment AC QR Qn+1 SC Example: -9 × -13 = 117 BR = 10111, BR + 1 = 01001 00000 10011 01001 01001 00100 11001 00010 01100 10111 11001 11100 10110 11110 01011 01001 00111 00011 10101

Subtract BR Add BR Subtract BR Ashr Ashr Ashr Ashr Ashr

Exercise

• Show the step by step multiplication

process using Booth algorithm when the

following binary numbers are multiplied.

Assume 5-bit registers that hold signed

numbers. The multiplicand in both cases is

(+15) × (+13)

(+15) × (-13)