Computer Achitecture and org - Busprotocols , Study notes of Computer Architecture and Organization

Detail Summery about Bus Protocols, PCI – Data Transfer, Data transfer signals on the PCI bus, A read operation on the PCI Bus, SCSI, Device configuration.

Typology: Study notes

2010/2011

Uploaded on 09/02/2011

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Bus Protocols
The essence of any bus is the set of rules by which data moves between devices.
This set of rules is called a “protocol.
- PCI (Peripheral Component Interconnect)
- SCSI (Small computer System Interconnect)
PCI:
-PCI bus is often referred as “local” bus which is designed to interface with different
microprocessor families, main memory, and a very wide range of I/O devices.
It can support either 32- bit or 64- bit data transfer with maximum clock rate of 66
MHZ and allows a data transfer rate up to 524 MB/s.
Basic transfer mode is burst transfer and it uses multiplexed address and data lines.
PCI bus architecture is a processor independent.
PCI bus is basically intended for attaching IO devices to a computer, but it has many
of the characteristics of a high performance system bus.
- PCI bus controller communicates independently with IO devices via PCI bus and
communicates with memory through system bus.
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Bus Protocols

The essence of any bus is the set of rules by which data moves between devices. This set of rules is called a “protocol.

  • PCI (Peripheral Component Interconnect)
  • SCSI (Small computer System Interconnect) PCI: -PCI bus is often referred as “local” bus which is designed to interface with different microprocessor families, main memory, and a very wide range of I/O devices. It can support either 32- bit or 64- bit data transfer with maximum clock rate of 66 MHZ and allows a data transfer rate up to 524 MB/s. Basic transfer mode is burst transfer and it uses multiplexed address and data lines. PCI bus architecture is a processor independent. PCI bus is basically intended for attaching IO devices to a computer, but it has many of the characteristics of a high performance system bus.
  • PCI bus controller communicates independently with IO devices via PCI bus and communicates with memory through system bus. .

High speed devices such as video terminals and fast network controllers that are connected directly to the PCI bus. IO devices intended to conform with other bus standards such as SCSI or ISA can also be interfaced to PCI bus via appropriate IO controllers, such as SCSI bus Controller An important feature that the PCI is a plug-and-play capability for connecting I/O devices. To connect a new device, the user simply connects the device interface board to the bus. PCI offers a number of significant performance and architectural advantages over previous busses (i.e. 8 bit XT Bus ,16-bit bus – ISA bus, 32-bit – EISA bus)

  • Speed.
  • Reliability. -Multiple masters.
  • Configurability.

PCI – Data Transfer

The bus supports three independent address spaces

-Memory

-I/O

-Configuration

  • A 4-bit command that accompanies the address identifies which of the

three spaces is being used in a given data transfer operation.

  • In earlier buses, the master maintains the address information on the

bus until data transfer is completed. But this is not necessary

  • The address is needed only long enough for the slave to be selected.
  • The slave can store the address in its internal buffer.
  • Thus the address is needed for one clock cycle only, freeing the bus for

sending the data in subsequent clock cycles => reduces cost

  • A master is called an initiator in PCI terminology – DMA controller.

The addressed device that responds to commands is target.

Data transfer signals on the PCI bus

Name Function

CLK A 33-MHz or 66 MHz clock

FRAME# sent by initiator to indicate the duration of

a transaction

AD 32 address/data lines (may be optionally

increased to 64)

C/BE# 4 command/byte enable lines (8 for a 64-

bit bus)

IRDY#, TRDY# Initiator ready and target ready signals

DEVSEL# a response from the device

indicating that it has recognized its

address and ready for a data transfer

transaction

IDSEL# Initialization Device Select

Signals whose name ends with the symbol # are asserted

when in the low voltage state

Example of a Bus transaction

  • (^) Processor reads 4 32-bit words from the memory.
  • (^) Initiator – processor, target – memory
  • (^) A complete transfer operation on the bus, involving an address and a

burst of data is called transaction

  • (^) Individual word transfers within transaction are called phases
  • (^) Clock cycle 1 – FRAME# is asserted by the processor, address is sent

on AD lines, a command on the C/BE# lines

  • (^) Clock cycle 2 – AD bus lines are off => processor removes address from

AD lines, DEVSEL# is asserted, C/BE# (4 lines are associated with one

byte on the AD lines.

  • (^) The initiator sets one or more of the C/BE# lines to indicate which byte

lines are used for transferring data

  • (^) Clock cycle 3 – IRDY# is asserted to indicate that initiator is ready to

receive the data, TRDY# - to indicate that target has data to send at this

time.

  • (^) The initiator loads the data into its input buffer at the end of the clock

cycle.

  • (^) Clock cycle 4 to 6 – target sends 3 more words
  • (^) Frame# is negated during clock cycle 5
  • (^) After sending the 4th^ word in CLK cycle 6, the target disconnect drivers

and negates DEVSEL# at the beginning of CLK cycle 7.

SCSI

  • Small Computer System Interface , or SCSI (pronounced scuzzy ), is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. -SCSI is most commonly used for hard disks and tape drives, but it can connect a wide range of other devices, including scanners and CD drives.(8 or 16 devices can be attached to a single bus) -It was originally designed to transfer data a byte at a rates up to 5MB/s Its data bus is 8 bits wide and also used to transfer addresses. -Recent extensions to the original SCSI standard have wider data buses( and 32),more control features and high data transfer rate i.e 320MB/s,640MB/s. The maximum transfer rate on a given bus is often a function of the length of the cable and the number of devices connected

-SCSI controller uses DMA to transfer data packets from the main memory to the device, or vice-versa. A packet may contain a block of data, commands from the processor to the device or status information about the device. -A controller connected to a SCSI bus is one of the two types – initiator or a target -An initiator has the ability to select a particular target and send commands specifying the operations to be performed. Initiator – SCSI controller, target – disk controller The initiator establishes a logical connection with the intended target. While a particular connection is suspended, other devices can use the bus to transfer information. This ability to overlap data transfer requests is one of the key features of the SCSI bus that leads to its high performance