Computer Architecture and Assembly Language, Exams of Computer Architecture and Organization

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EEE 230

Computer Organization & Assembly

Language Programming

MIDTERM READINESS EXAM

GUIDE

Q & S

1. Which of the following best describes a Harvard architecture?
   • A. Single memory for instructions and data
   • B. Separate memories for instructions and data
   • C. Utilizes cache memory
   • D. Supports virtual memory
   • Correct Answer : B
   • Rationale: Harvard architecture has separate storage and buses for instructions and data, allowing simultaneous access.
2. In the context of assembly programming, what does the term 'operand' refer to?
   • A. The operation to be performed
   • B. The data on which the operation is performed
   • C. The result of the operation
   • D. The address of the instruction
   • Correct Answer : B
   • Rationale: An operand is the data that the instruction operates on, which can be a constant value, a register, or a memory address.
3. Which of the following ISA (Instruction Set Architecture) features is crucial for optimizing pipelining performance?
   • A. Load/Store architecture
   • B. Complex Data Types
   • C. Non-pipelined execution
   • D. Multi-cycle instructions
   • Correct Answer : A
   • Rationale: A load/store architecture minimizes dependencies that could stall the pipeline, improving

than _______ but slower than _______.

• Correct Answer : RAM, Registers
• Rationale: Cache memory sits between the CPU registers and RAM, providing a speed increase compared to RAM but is slower than CPU registers.

8. The _______ specifies how inputs and outputs interact with the CPU, defining the architecture interface.

• Correct Answer : I/O Architecture
• Rationale: The I/O Architecture outlines how the CPU communicates with peripheral devices.

9. In assembly language, the _______ instruction is often used to create loops by repeating processes until a condition is met.

• Correct Answer : LOOP or conditional jump
• Rationale: The LOOP instruction, or conditional jumps, allows branching in execution for repeatable processes.

10. The process of converting high-level programming code into machine code is known as _______.

• Correct Answer : Compilation
• Rationale: Compilation is the process of translating high-level code into machine-readable format.

True/False Questions

11. True/False: A microcontroller can be programmed in assembly language just like a microprocessor.

• Correct Answer : True
• Rationale: Both microcontrollers and microprocessors can execute assembly language, though microcontrollers

often have system-level functions integrated.

12. True/False: The ALU (Arithmetic Logic Unit) performs arithmetic operations but cannot handle logical operations.
    • Correct Answer : False
    • Rationale: The ALU performs both arithmetic and logical operations.
13. True/False: Assembly language is considered a high- level programming language.
    • Correct Answer : False
    • Rationale: Assembly language is a low-level programming language that is closer to machine code compared to high-level languages.
14. True/False: RISC processors usually use a large number of complex instructions.
    • Correct Answer : False
    • Rationale: RISC (Reduced Instruction Set Computer) typically uses a small number of simple instructions, which allows for higher efficiency.
15. True/False: A well-optimized assembly program can outperform a similar program written in a high-level language.
    • Correct Answer : True
    • Rationale: Optimized assembly code can closely match the hardware, offering better performance than high- level code due to less abstraction.

Multiple Response Questions

16. Which of the following are advantages of using

19. Which of the following are types of addressing modes in assembly language? (Select all that apply)
    • A. Immediate
    • B. Direct
    • C. Indirect
    • D. Absolute
    • Correct Answer s: A, B, C
    • Rationale: Immediate, direct, and indirect addressing modes are all valid methods for specifying operands in assembly language.
20. Which of the following are methods to optimize instruction execution in assembly programming? (Select all that apply)
    • A. Minimizing the use of jumps
    • B. Loop unrolling
    • C. Using recursive functions
    • D. Register allocation optimization
    • Correct Answer s: A, B, D
    • Rationale: Minimizing jumps, employing loop unrolling, and optimizing for register usage are effective strategies for code optimization.

Additional Questions

21. Which assembly language construct allows for conditional execution based on previous results?
    • Correct Answer : Conditional branches
    • Rationale: Conditional branches allow program execution to change based on outcomes of previous instructions.

22. What is the primary function of the instruction decode stage in the CPU pipeline?
    • Correct Answer : To interpret the fetched instruction and prepare for execution.
    • Rationale: The instruction decode stage is crucial for understanding what operations to perform on which data.
23. What is the typical size of a word in a 32-bit architecture?
    • Correct Answer : 4 bytes
    • Rationale: In a 32-bit architecture, each word is typically 32 bits, which is equivalent to 4 bytes.
24. What does the status register in a CPU typically contain?
    • Correct Answer : Flags that indicate the outcome of operations.
    • Rationale: The status register or flag register indicates results from arithmetic or logic operations, such as overflow, zero, or negative results.
25. Which of the following are types of cache memory? (Select all that apply)
    • A. L1 Cache
    • B. L2 Cache
    • C. System Cache
    • D. Disk Cache
    • Correct Answer s: A, B, D
    • Rationale: L1 and L2 are levels of cache memory found in the CPU, while disk cache improves data access speeds on storage devices.
26. Which assembly language instruction is commonly

components C) To store data temporarily D) To execute instructions Correct Answer : B Rationale: The Control Unit directs the operation of the processor and manages data flow between the CPU and other components. Fill-in-the-Blank: The __ architecture allows for greater flexibility in instruction set design, making it easier to implement complex instructions. Correct Answer : RISC (Reduced Instruction Set Computer) Rationale: RISC architecture is characterized by a small set of simple instructions, promoting efficiency and speed. True/False: The Stack is used primarily for dynamic memory allocation in a program. Correct Answer : False Rationale: The Stack is primarily used for function calls and local variable storage, while dynamic memory allocation is handled by the Heap. Multiple Response: Which of the following are advantages of using Assembly Language over high-level programming languages? (Select all that apply) A) Greater control over hardware B) More efficient use of system resources C) Easier syntax D) Faster execution time Correct Answer s: A, B, D Rationale: Assembly Language allows for more direct hardware manipulation, leading to efficient resource use

and faster execution, but it does not offer easier syntax compared to high-level languages. Multiple Choice: In a pipelined architecture, what is the primary benefit achieved? A) Reduced power consumption B) Increased instruction throughput C) Simplified instruction decoding D) Enhanced memory access speed Correct Answer : B Rationale: Pipelining increases instruction throughput by allowing multiple instructions to be processed simultaneously in different stages. Fill-in-the-Blank: The process of converting high-level language code into machine code is known as __. Correct Answer : Compilation Rationale: Compilation is the translation of high-level language code into a machine-readable format. True/False: The ALU (Arithmetic Logic Unit) is responsible for performing both arithmetic and logical operations. Correct Answer : True Rationale: The ALU performs all arithmetic and logical operations required by the CPU. Multiple Choice: Which of the following registers is used to hold the address of the next instruction to be executed? A) Program Counter (PC) B) Instruction Register (IR) C) Accumulator (ACC) D) Stack Pointer (SP) Correct Answer : A

Correct Answer : B Rationale: The bus serves as a communication pathway that connects various components of the computer system. Fill-in-the-Blank: The __ addressing mode uses the value of the operand directly in the instruction. Correct Answer : Immediate Rationale: Immediate addressing mode involves using a constant value as the operand directly within the instruction. True/False: In a memory hierarchy, Cache memory is generally slower than RAM. Correct Answer : False Rationale: Cache memory is faster than RAM due to its proximity to the CPU and its design for high-speed access. Multiple Response: Which of the following are characteristics of a RISC architecture? (Select all that apply) A) Fixed instruction length B) Complex addressing modes C) Large number of general-purpose registers D) Load/store architecture Correct Answer s: A, C, D Rationale: RISC architectures typically use fixed instruction lengths, a larger number of general-purpose registers, and a load/store architecture to simplify instruction execution. Multiple Choice: What is the maximum number of bits in a 32 - bit address bus? A) 16 B) 32

C) 64

D) 128

Correct Answer : B Rationale: A 32-bit address bus can address 2^32 distinct memory locations, which corresponds to 32 bits. Fill-in-the-Blank: The instruction set architecture (ISA) acts as a bridge between __ and hardware. Correct Answer : Software Rationale: ISA defines how software interacts with the hardware, specifying the instructions that a processor can execute. True/False: The purpose of the Memory Management Unit (MMU) is to translate virtual addresses to physical addresses. Correct Answer : True Rationale: The MMU is responsible for translating virtual memory addresses to physical memory addresses, allowing for effective memory management. Multiple Response: Which of the following techniques can improve CPU performance? (Select all that apply) A) Pipelining B) Multi-core processing C) Increasing clock speed D) Reducing cache size Correct Answer s: A, B, C Rationale: Pipelining, multi-core processing, and increasing clock speed are all techniques used to enhance CPU performance, while reducing cache size would likely decrease performance.

3. True/False: An assembler translates assembly language into machine code. Correct Answer : True Rationale: An assembler is a tool that converts assembly language, which is human-readable, into machine code that can be executed by the CPU.
4. Multiple Response: Which of the following are types of cache memory? (Select all that apply) a) Instruction cache b) Data cache c) Level 1 cache d) Level 2 cache Correct Answer s: a) Instruction cache, b) Data cache, c) Level 1 cache, d) Level 2 cache Rationale: Cache memory can be categorized by its location and function. Instruction cache holds the instructions, data cache holds data, and Level 1 and Level 2 caches refer to their position in the hierarchy of speed and size.
5. Multiple Choice: In a pipelined CPU architecture, what does the term 'hazard' refer to? a) A failure in the pipeline due to incorrect data being processed b) A situation that could cause a stall in the pipeline's execution c) An error in the assembly code d) A physical defect in the CPU Correct Answer : b) A situation that could cause a stall in the pipeline's execution Rationale: Hazards in pipelining can lead to stalls or incorrect operations if not handled properly. They are

situations that prevent the next instruction in the pipeline from executing in the following cycle.

6. Fill-in-the-Blank: The process of combining several small operations into a single complex instruction is known as _______. Correct Answer : microprogramming Rationale: Microprogramming is a technique that allows for a simpler hardware design by using a sequence of microinstructions to represent complex instructions.
7. True/False: RISC architectures typically use a large number of instructions with complex functionalities. Correct Answer : False Rationale: RISC (Reduced Instruction Set Computer) architectures use a smaller set of instructions with the aim of optimizing the instructions' execution time.
8. Multiple Response: Which of the following are characteristics of a superscalar processor? (Select all that apply) a) Multiple instruction issue b) Instruction-level parallelism c) Single instruction stream d) Complex instruction set Correct Answer s: a) Multiple instruction issue, b) Instruction-level parallelism Rationale: Superscalar processors can issue multiple instructions per clock cycle and exploit instruction-level parallelism to improve performance.
9. Multiple Choice: What is the purpose of a register file in a CPU?