Computer Architecture and Organization - instruction Formats - Saritha, Study notes of Computer Architecture and Organization

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Computer Architecture &

Organization

Unit I- Fundamentals of computer

Architecture

• (^) Organization of von Neumann machine
• (^) Instruction formats
• (^) The fetch/execute cycle
• (^) Instruction decoding and execution
• (^) Registers and registers files
• (^) Instruction types and addressing modes
• (^) Subroutine call and return mechanisms
• (^) Programming in assembly language
• (^) I/O techniques and interrupts
• (^) Other design issues

Instruction Formats

• (^) A 3 address instruction specifies memory addresses for both

operands and the result

• (^) R  Op1 op Op
• (^) A 2 address instruction overwrites one operand in memory with the

result

• (^) Op2  Op1 op Op
• (^) A 1 address instruction has a processor, called the accumulator

register to hold one operand & the result (no addr. needed)

• (^) Acc  Acc op Op
• (^) A 0 address instruction uses a CPU register stack to hold both

operands and the result

• (^) TOS  TOS op SOS
• (^) where TOS is Top Of Stack, SOS is Second On Stack)
• (^) The 4-address instruction, hardly ever seen, also allows the address

of the next instruction to specified explicitly.

4-Address Instruction

• The 4-address instruction:

• Explicit addresses for operands, results

and next instruction

• Example assumes 24-bit address; Each

address requires 3 bytes ,so it will require

• 4X3+1= 13 bytes to encode a 4-address

ALU instruction.

• (^) Let us count the number of memory accesses required when the instruction executes
• (^) Example
• (^) 4-address instruction:
• (^) Five words will be transferred to the CPU when the instruction itself is fetched.= 5
• Then the two words representing the operands themselves need to be

fetched into the CPU = 2

• (^) And after the addition has been performed, the result needs to be written back to

memory = 1

• (^) Total= 08
• Because of the large instruction word size and number of memory accesses the 4-

address machine and instruction format is not seen machine design.

• (^) Although the 4-address structure is used internally in some implementations of

computer control units. This kind of controller implementations is known as micro

coded Control.

4 address Instruction

3-Address Instruction

• (^) 3-Address instruction:
  • (^) Address of next instruction kept in processor state register—the PC

(Except for explicit Branches/Jumps)

• (^) Rest of addresses in instruction
• (^) This Instruction will require 3X3+1= 10 bytes to encode a 3-address

ALU instruction.

The number of memory access are required for a 3-address

instruction:

• (^) Four words will be transferred to the CPU when the instruction itself is

fetched.= 4

• (^) Then the two words representing the operands themselves need to be

fetched into the CPU = 2

• (^) And after the addition has been performed, the result needs to be

written back to memory = 1

Total =

The 2-Address, Machine and Instruction

Format

The 2-Address, Machine and Instruction

Format

• (^) 2-address Instruction :
  • (^) Result overwrites Operand 2
  • (^) Needs only 2 addresses in instruction but less choice in placing data
  • (^) This Instruction will require 2X3+1= 7 bytes to encode a 2-address ALU

instruction.

The number of memory access are required for a 2-address

instruction:

• (^) Three words will be transferred to the CPU when the instruction itself

is fetched. = 3

• (^) Then the two words representing the operands themselves need to be

fetched into he CPU and after the addition has been performed, Result

overwrites Operand =

• (^) Total= 06
• (^) add Op1Addr Op2Addr

1-Address Instruction

• (^) 1-address Instruction :
  • (^) Special CPU register, the accumulator, supplies 1 operand and stores result
  • (^) One memory address used for other operand
  • (^) Need instructions to load and store operands:
    • LDA OpAddr
    • (^) STA OpAddr
• (^) This Instruction will require 1X3+1= 4 bytes to encode a 1-address ALU

instruction

The number of memory access are required for a 1-address instruction:

• Two words will be transferred to the CPU when the instruction itself is fetched =

2

• (^) Then the one word representing the operand itself need to be fetched into

the CPU register and the accumulator, supplies 1 operand and stores

result = 1

• (^) Total=

The 0-Address, or Stack, Machine and

Instruction Formats

• End of Lecture