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Solutions to discussion 9 of cs232 course, which involves analyzing cache behavior and performance. It includes the determination of hits and misses for a given series of address references, calculation of average memory access time (amat) for different cache levels, and an explanation of the impact of cache misses on overall performance.
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CS232 Discussion 9: Model Solutions
Index Cache Contents 0 16 64 48 1 2 2 3 3 19 3 4 4 5 21 6 22 6 7 8 9 10 11 11 27 11 12 13 13 14 15
AM AT = Hit time + (Miss rate × Miss penalty) = 1 cycle + (3% × 20 cycles) = 1.6 cycles
Let I be the total number of instructions.
Memory Stall Cycles = Memory Accesses × Miss rate × Miss penalty = 0. 33 I × 0. 03 × 20 = 0. 198 I
If the cache was perfect and never missed, the AMAT would be one cycle. But even with just a 3% miss rate, the AMAT here increases 1.6 times!
CS232 Discussion 9: Model Solutions
Find the average memory access time (AMAT) for both the L2 and L1 cache.
Table 1. Cache Parameters for Q L1 L Data Size 32KB 256KB Block Size 8bytes 32bytes Associativity Direct-mapped 4-way Hit Time 1 cycle 19 cycles Miss Rate 5% 2%
Solution: Per assumption, it takes 50 cycles to retrieve 32 bytes of data from main memory, so this is the miss penalty for the L2 cache. AMATL2 = 19 cycles + (0.02 × 50 cycles) = 20 cycles The L2 AMAT is 20 cycles. AMAT of L2 is the miss penalty for the L1 cache. When there is a miss in the primary cache, the average time to get data from the L2 is 20 cycles. AMATL1 = 1 cycle + (0.05 × 20) cycles = 2 cycles. So, the AMAT of the L1 cache is 2 cycles.