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William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory

Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only memory Not possible Masks Nonvolatile Programmable ROM (PROM) Electrically Erasable PROM (EPROM) Read-mostly memory UV light, chip-level Electrically Erasable PROM (EEPROM) Electrically, byte-level Flash memory Electrically, block-level

Memory Cell Operation

Dynamic RAM

• (^) Bits stored as charge in capacitors
• (^) Charges leak
• (^) Need refreshing even when powered
• (^) Simpler construction
• (^) Smaller per bit
• (^) Less expensive
• (^) Need refresh circuits
• (^) Slower
• (^) Main memory
• (^) Essentially analogue —Level of charge determines value

DRAM Operation

• (^) Address line active when bit read or written — (^) Transistor switch closed (current flows)
• (^) Write — (^) Voltage to bit line - (^) High for 1 low for 0 — (^) Then signal address line - (^) Transfers charge to capacitor
• (^) Read — (^) Address line selected - (^) transistor turns on — (^) Charge from capacitor fed via bit line to sense amplifier - (^) Compares with reference value to determine 0 or 1 — (^) Capacitor charge must be restored

Static RAM

• (^) Bits stored as on/off switches
• (^) No charges to leak
• (^) No refreshing needed when powered
• (^) More complex construction
• (^) Larger per bit
• (^) More expensive
• (^) Does not need refresh circuits
• (^) Faster
• (^) Cache
• (^) Digital —Uses flip-flops

Static RAM Operation

• (^) Transistor arrangement gives stable logic state
• (^) State 1 —C 1 high, C 2 low —T 1 T 4 off, T 2 T 3 on
• (^) State 0 —C 2 high, C 1 low —T 2 T 3 off, T 1 T 4 on
• (^) Address line transistors T 5 T 6 is switch
• (^) Write – apply value to B & compliment to B
• (^) Read – value is on line B

SRAM v DRAM

• (^) Both volatile —Power needed to preserve data
• (^) Dynamic cell —Simpler to build, smaller —More dense —Less expensive —Needs refresh —Larger memory units
• (^) Static —Faster —Cache

Types of ROM

• (^) Written during manufacture —Very expensive for small runs
• (^) Programmable (once) —PROM —Needs special equipment to program
• (^) Read “mostly” —Erasable Programmable (EPROM) - (^) Erased by UV —Electrically Erasable (EEPROM) - (^) Takes much longer to write than read —Flash memory - (^) Erase whole memory electrically

Organisation in detail

• (^) A 16Mbit chip can be organised as 1M of 16 bit words
• (^) A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on
• (^) A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array —Reduces number of address pins - (^) Multiplex row address and column address - (^) 11 pins to address (2^11 =2048) - (^) Adding one more pin doubles range of values so x capacity

Typical 16 Mb DRAM (4M x 4)

Packaging

1MByte Module Organisation

Interleaved Memory

• (^) Collection of DRAM chips
• (^) Grouped into memory bank
• (^) Banks independently service read or write requests
• (^) K banks can service k requests simultaneously