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وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi Academic Year :2019/
Second term
Cache Memory
Subject: Computer Architecture
Research Code
Supervised By
Dr. Ahmed Ibrahim / Dr. Abas Rostom
Student Complete Name
Section / Grade
Class 7 / الفرقة الثالثة
ID Number
pass fail
C 310/
وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi
Subject: Computer Architecture
Research Title: Cache Memory
Academic Year 2019/
Research Code
pass fail
C 310/
وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi
- Both are temporary memories. However, they vary by speed, size, and value. 1. Placement: Cache is sometimes mainly on the central processor chip itself. The main memory (RAM) is placed on the motherboard and is connected to the C.P.U. via the Memory Bus. 2. Speed: As a result of the cache being nearer to the C.P.U., it's a lot quicker than RAM. Every read access on the main memory needs to travel via the Memory Bus whereas the C.P.U. cache is right there. 3. Size: The scale of the cache is far less compared thereto of the main memory. The scale of the main Memory or RAM in today's computers could be a few GBs. Whereas, the scale of cache could be a few MBs. 4. Cost: Cache is costlier than the main memory. 5. Why own another temporary memory after we have already got low cost and huge main memory?
- It is especially to boost speed; the cache is there to cut back the average memory access time for the C.P.U. 6. Mostly cache is split into three levels referred to as L1 cache (level 1), L2 cache (level 2), and L3 cache (level 3). L1 is the nearest to the C.P.U. and additionally the foremost costly. Whenever there's a memory read request, L1 is checked 1st, then L2, then L3 and so the main memory. Fig )b(.
3. MAPPING MEMORY TO CACHE
-Cache Mapping Technique: - the various Cache mapping technique they're as follows: - (1) Direct Mapping , (2) Associative Mapping, (3) Set Associative Mapping web [1] Consider a cache consisting of 128 blocks of every 16 words, for a total of 2048 works, and assume that the main memory is addressable by 16-bit address. The main memory is 64K which can be viewed as 4K blocks of 16 words each. Direct Mapping: - I. The best way to know the cache locations which keep Memory blocks is by using direct Mapping technique. II. During this block J of the main memory maps on to block J mod 128 of the cache. Therefore, the
وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi main memory blocks 0, 128, 256…. is loaded into the cache is kept at block 0. Block 1, 129, 257…. are kept at block 1 and so on. III. The placement of a block within the cache is decided from the memory address. The memory address is split into three fields, the lower 4-bits selects one among the 16 words in a block. IV. Once the new block enters the cache, the 7-bit cache block field determines the cache positions within which this block should be kept. V. The upper order 5-bits of the memory address of the block are kept in 5 tag bits related to its location in the cache. They determine which one of the 32 blocks that are mapped into this cache position are presently resident within the cache. VI. It's simple to implement, however not flexible. Associative Mapping: - I. This can be a lot of a versatile mapping method, in which the main memory block can be placed into any cache block position. II. In this, 12 tag bits are needed to spot a memory block once it's resident within the cache. III. The tag bits of an address received from the processor are compared to the tag bits of every block of the cache to check if the specified block is there. This can be referred to as Associative Mapping technique. IV. The value of an associated mapped cache is over the price of direct-mapped due to the necessity to look at all 128 tag patterns to see whether or not a block is in the cache. This can be referred to as associative search. Set-Associated Mapping: - I. It's a mix of direct and associative mapping technique. II. Cache blocks are grouped into sets and mapping allows each block of main memory to reside into any block of a selected set. Therefore, the problem of direct mapping is relieved, at a similar time, the hardware value is reduced by decreasing the size of the associative search.
وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi Random Replacement )RR(: -
- Randomly selects a block and removes it to make space when needed, and it doesn’t keep any access history. RESULTS AND DISCUSSION : CONCLUSIONS: 1. Cache memory sits between the C.P.U. and the main memory, it’s a lot quicker than RAM, the cache is there cutting back the average memory access time for the C.P.U... The size of the cache is far less compared to the main memory. The cache is costlier than the main memory. The more cache, the less time the computer spends accessing slower main memory. 2. In direct mapping, each block in memory is mapped to only one line which makes it faster, but less versatile. 3. In associative mapping, a new cache line can be placed anywhere in the cache. It is slower than other types of mappings but it is highly versatile. 4. Set-associated mapping, it's a mix of direct and associative mapping technique. In this technique, a new cache line is to be placed in any of the ‘N’ cache lines. This is relatively faster and relatively versatile when compared to the other mapping techniques. 5. The first in first out replacement algorithm removes the block that has been in the cache for the longest time. 6. In the least recently used algorithm, the block which has not been referenced for the longest time is removed from the cache. 7. Random replacement, randomly selects a block and removes it to make space when needed, and it doesn’t keep any access history. REFERENCES: Books: 1- Hill, M.D., 1987. Aspects of cache memory and instruction buffer performance (No. UCB/CSD-87-381). CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICALENGINEERINGANDCOMPUTERSCIENCES. 2- Knotts, B.W., NCR Corp, 1997. Coherent copyback protocol for multi-level cache memory systems. U.S. Patent 5,671,391.
وزارىلاعلا ميلعتلا ة التعليىلاعلا م العالى األكاديمية الحديثة لعلورتويبمكلا م الكمبيوتر وتكنولوجيا اإلدارىلاعلا ميلعتلا ة بالمعادى Modern Academy For Computer Science and Management Technology In Maadi Websites: 1- https://www.quora.com/What-are-the-advantages-disadvantages-of-different-Cache- Mapping-architectures-Direct-Mapped-Set-Associative-Fully-Associative, 14/5/
