INPUT/OUTPUT ORGANIZATION
•Accessing I/O Devices
•I/O interface
•Input/output mechanism
Memor
y
-ma
pp
ed I
/
O
y
pp
/
Programmed I/O
Interrupts
Direct
Memory
Access
Direct
Memory
Access
•Buses
Synchronous Bus
Asynchronous Bus
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I/O Devices and Bus Design: A Comprehensive Guide, Lecture notes of Computer Architecture and Organization
Basic Structure Of Computers: Functional unit, Basic Operational concepts, Bus structures, System Software, Performance, The history of computer development
Typology: Lecture notes
2017/2018
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INPUT/OUTPUT ORGANIZATION
-^ Accessing I/O Devices •^ I/O interface •^ Input/output mechanism
Memory-mapped I/O
y^
pp^
Programmed I/OInterruptsDirect Memory AccessDirect Memory Access
-^ Buses
Synchronous BusAsynchronous Bus
I/O in CO and O/S
•^
Programmed I/O
-^
Interrupts
-^
DMA
(Direct memory Access)
Accessing I/O Devices
-^ Most modern computers use single bus arrangementfor connecting I/O devices to CPU & Memory •^ The bus enables all the devices connected to it toexchange informationexchange information •^ Bus consists of 3 set of lines :
Address, Data, Control
-^ Processor places a particular address (unique for anI/O Dev.) on address lines •^ Device which recognizes this address responds to thecommands issued on the Control linescommands issued on the Control lines •^ Processor requests for either Read / Write •^ The data will be placed on Data lines
Hardware to connect I/O devices
t^
b to bus
-^ Interface Circuit^ –
Address Decoder – Control Circuits– Control Circuits – Data registers – Status registers
-^ The Registers in I/O Interface – buffer and control •^ Flags in Status Registers
like SIN
SOUT
-^ Flags in Status Registers,
like SIN, SOUT
-^ Data Registers,
like Data-IN, Data-OUT
Input Output
h^
i
-^ Memory mapped I/O •^ Programmed
I/O
mechanism
Programmed I/O • Interrupts • DMA
(Direct memory Access)
A bus generally contains a set of control lines and a set of data lines.
The control lines are used to signal requests and acknowledgments, and to indicate what type of information ison the data lines. The control lines are used to indicate whatthe bus contains and to implement the bus protocol.
The data lines of the bus carry information between the source and the destination. This information may consistof data, complex commands, or addresses.
di i
ll^
l^
ifi^ d
Buses are traditionally classified as processor-memory buses or I/O buses or special purposed buses (Graphics, etc. ).Processor memory buses are short, generally high speed, andmatched to the memory system so as to maximize memory-processor bandwidth.
I/O b
b^
t^
t^
b^ l
th^
h
I/O buses, by contrast, can be lengthy, can have many types of devices connected to them, and often have a widerange in the data bandwidth of the devices connected to them.I/O buses do not typically interface directly to the memory butuse either a processor-memory or a backplane bus to connectto memory.
The two basic schemes for communication on the bus are synchronous and asynchronous.
If a bus is synchronous (e.g. Processor-memory), it includes a clock in the control lines and a fixed protocol forcommunicating that is relative to the clock.
g This type of protocol can be implemented easily in a small finite state
machine. Because the protocol is
predetermined and involves little logic, the bus can run veryfast and the interface logic will be small.
Synchronous buses have two major disadvantages:Synchronous buses have two major disadvantages:
- First, every device on the bus must run at the same clockrate.- Second, because of clock skew problems, synchronous busescannot be long if they are fast.
A^
h^
b^
i^
t^ l^
k^ d
It^
d^ t
An asynchronous bus is not clocked. It can accommodate a wide variety of devices, and the bus can be lengthened withoutworrying about clock skew or synchronization problems.
To coordinate the transmission of data between sender and receiver, an asynchronous bus uses a handshaking protocol
Three special control lines required for hand-shaking:ReadReq: Used to indicate a read request for memory. The addressis put on the data lines at the same time.D^ t^
Rd^
U^
d t^
i^ di
t^
th^ t th
d^
t^
d i^
d^
th
DataRdy: Used to indicate that the data word is now ready on thedata lines; asserted by: Output/Memory and Input/I_O Device.Ack: Used to acknowledge the ReadReq or the DataRdy signal of theAck: Used to acknowledge the ReadReq or the DataRdy signal of theother party.
Memory mapped I/O
-^ I/O devices and the memory share
the same address space
the
-^ I/O devices and the memory share
the same address space, the
arrangement is called
Memory-mapped I/O.
-^ In Memory
- mapped I/O portions of address space are assigned -^ In Memory
- mapped I/O portions of address space are assigned
to I/O devices and reads and writes to those addresses areinterpreted as commands to the I/O device.“DATAIN” is the address of the input buffer associated with thekeyboard.-
Move
DATAIN, R
reads the data from DATAIN and stores them into processorregister R0;register R0;
-^ Move
R0,
DATAOUT
sends the contents of
register R0 to location DATAOUTg
Option of special I/O address space or incorporate as a part of memory address space (address bus is same always).
DATAINDATAOUTSTATUS
DIRQ
KIRQ
SOUT
SIN
DEN
KEN
CONTROL
7
6
5
4
3
2
1
0
DEN
KEN
I/O operation involving keyboard and display devicesRegisters: DATAIN, DATAOUT, STATUS, CONTROLFlags:
SIN, SOUT
- Provides status information for keyboard
and display unitKIRQ, DIRQ – Keyboard, Display Interrupt request bitsDEN, KEN
–Keyboard, Display Enable bits
Programmed I/O
-^ CPU has direct control over I/O
S^
i^
t^ t
-^ Sensing status –^ Read/write commands –^ Transferring dataTransferring data -^ CPU waits for I/O module to^ complete operation •^ Wastes CPU time•^ Wastes CPU time
A ISA program to read one line from the keyboard, store it in
memory buffer
and echo it back to the display
memory buffer, and echo it back to the display
The disadvantage of polling is that it can waste a lot of processor time because processors are so much faster thanI/O devicesI/O devices.
The processor may read the Status register many times, only to find that the device has not yet completed aonly to find that the device has not yet completed acomparatively slow I/O operation, or that the mouse has notbudged since the last time it was polled.
When the device completes an operation, we must still read the status to determine whether it (I/O) was successful.
Overhead in a polling interface lead to the invention of
interrupts
to notify the processor when an I/O
invention of
interrupts
to notify the processor when an I/O
device requires attention from the processor.
Interrupt driven I/O
employs I/O interrupts to
Interrupt-driven I/O, employs I/O interrupts to indicate to the processor that an I/O device needs attention.
When a device wants to notify the processor that it hasWhen a device wants to notify the processor that it has completed some operation or needs attention, it causes theprocessor to be interrupted.