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Computer Organization and Architecture Quiz, Quizzes of Computer Architecture and Organization

A quiz on the topic of computer organization and architecture, administered by the department of computer science and engineering at the abv - indian institute of information technology, gwalior. The quiz consists of 10 questions, each worth 0.5 marks, covering various aspects of computer architecture such as memory addressing, cache organization, and processor components. The quiz is designed to assess the students' understanding of the fundamental concepts in computer organization and architecture. Detailed information about the quiz, including the faculty member responsible, the course code, and the instructions for the students. By analyzing this document, one can gain insights into the curriculum, teaching methods, and assessment practices employed in the computer science and engineering program at the abv - indian institute of information technology, gwalior.

Typology: Quizzes

2022/2023

Uploaded on 11/27/2023

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Download Computer Organization and Architecture Quiz and more Quizzes Computer Architecture and Organization in PDF only on Docsity! ABV - Indian Institute of Information Technology, Gwalior Department of Computer Science and Engineering Quiz # 1 : ITIT-2103 ”Computer Organization and Architecture” Faculty : Dr. Deepak Kumar Dewangan Name : Roll No. : Sem/Batch : Note: Overwriting and usage of pencil will not be evaluated. There are 10 questions to be solved and each question carry 0.5 marks. 1. Which of the following is equal to 4 bits? (a) Byte (b) Nibble (c) Record (d) All of the above 2. An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit ad- dress. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET. The number of bits in the TAG is . (a) 18 (b) 19 (c) 20 (d) 21 3. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. As- sume that the main memory is byte addressable and uses a 32-bit address. How many bits are re- quired for the Tag and the Index fields respectively in the addresses generated by the processor? (a) 28 bits and 4 bits (b) 24 bits and 4 bits (c) 24 bits and 0 bits (d) 28 bits and 0 bits 4. Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The numbers of bits in the TAG, LINE and WORD fields are respectively (a) 9, 6, 5 (b) 7, 7, 6 (c) 7, 5, 8 (d) 9, 5, 6 1 Score : Date : 06.09.2023