Computer Achitecture and org- Revision, Study notes of Computer Architecture and Organization

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Revision

Quiz

1. Distinguish between Computer Architecture and

Organization.

2. What is the basic function of a computer?

3. List the characteristics of IAS computer

4. In IAS computer, IAS stands for………..

5. ………… Register contains the 8-bit opcode instruction

being executed

6. ………………Register employed to temporarily hold the

right –hand instruction from a word in memory.

7. ………………..contains the address of the next instruction

–pair to be fetched from memory

8. …………………employed to temporarily hold operands

and results of ALU operations

Problems

1. Interpret the following expression for IAS computer flow of operations.

X = (A – B + C * (D * E - F))

Where data variables are available from location address 500 onwards and

program can be stored at memory location 200 onwards.

2. Write an Assembly language programming for the following expressions

using IAS computer Instruction set and interpret to the flow of IAS

computer

1. A=(B-C)*D

2. A=B*(C+D)

3. A=(B-C)/D

4. A=B/(C+D)

5. A=-(B+C-D)

6. A=(B*2)/

Make necessary assumptions

Problems

• Write an assembly language programming for

the following code fragment and Interpret to IAS

computer flow of operations.

if(x=0)

c=a*b;

else

c=a/b;

Where

Data variables are available from location address

500 onwards and program can be stored at

memory location 200 onwards.

Write an appropriate assembly language code for the following operation and interpret to Von Neumann IAS architecture X=Y*Z Where X->40 bit data and Y->40 bit data Result would be more than 40 bit.

Solution for X=Y*Z

Assume that data variables ‘Y’ & ‘Z’ available

at memory locations 801 & 802

respectively. And X will be stored 803

onwards.

LOAD MQ, M(801) MQM[801]

MUL M(802) AC MQMQ * M[802]

STOR M(803) M[803]AC

LOAD MQ ACMQ

STOR M(804) M[804]AC

Match the following

1. LOAD, STORE, MOV

2. JNZ, JZ, JNP,JNN

3. Add, Sub, MUL

4. Jump, Goto, break, exit

5. AND, OR, NOT

6. IN(), OUT()

A. Data Processing

(Data Manipulation)

B. Data

Movement (Data

Transfer)

C. Control

(Program

Control)

• (^) Source and result operand can be in one of three areas :
  • (^) Main or Virtual Memory : As with next instruction references ,the

main or virtual mammary address must be supplied.

• (^) CPU Register : With rare exceptions ,a CPU contains one or

more registers that may be referenced by machine instructions.

If only one register exists ,reference to may be explicit.

• (^) I/O Device : The instruction must specify the I/O module and

device for the operation. If the memory –mapped I/O is used

.This is just another main or virtual memory address.

Quiz

1. Number of fields in 4-address, 3-address, 2-

address, 1-address and 0-address instructions

2. Define memory access.

3. Number of memory access for fetching 3-

address instruction

4. Number of memory accesses for executing a 4-

address instruction

5. List the ways to reduce the number of memory

accesses

Evaluate a = (b+c)*d - e

add a, b, c ab+c mpy a, a, d sub a, a, e aad aa-e load a, b ab add a, c mpy a, d aa+c aad sub a, e aa-e load b Accb add c mpy d AccAcc+c AccAcc*d sub e AccAcc-e store a aAcc push b push c add push d mpy push e sub pop a 3-Address 2-Address 1-Address 0-Address

load b Accb add c mpy d AccAcc+c AccAccd sub e AccAcc-e store a aAcc Memory to Store Memory to encode M/As to Fetch M/As to Execute Memory Traffic 23=6 1+(13)=4^2 1 2+1= 23=6 1+(13)=4^2 1 2+1= 23=6 1+(13)=4^2 1 2+1= 23=6 1+(13)=4^2 1 2+1= 23=6 1+(13)=4^2 1 2+1= 30 20 10 5 15 23=6 1+(13)=4^ 2 1 3 23=6 1+(13)=4^2 1 1 1 0 0 0 23=6 1+(13)=4^2 1 1 1 0 0 0 23=6 1+(13)=4^2 1 1 1 0 0 0 23=6 1+(1*3)=4^2 1 33 23 10 5 15 push b push c add push d mpy push e sub pop a

Instructio n Format Memory to Store Memory to Encode M/As to Fetch M/As to Execute Memory Traffic 4-Address 45 39 24 9 33 3-Address 36 30 12 9 21 2-Address 36 28 12 12 24 1-Address 30 20 10 5 15 0-Address 33 23 10 5 15 Summary of 3-,2-,1-, and 0-Addresss instruction programming

Using Registers

• Registers are located in CPU

• Operation with register will not a cost for a

memory Access.

• But registers are limited