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ECE 485 Final Project
Design and Implementation of a MIPS CPU
with Multicycle Datapath
(version 1.01)
Erdal Oruklu
Electrical and Computer Engineering Department
Illinois Institute of Technology
Chicago, IL 60616, USA
November 7, 2005
1 Introduction
In this project, you will design and your own custom RISC processor which is ba- sically a stripped down MIPS processor. The goal of this project is provide you a more practical, hands-on approach to computer architecture design problems. You will learn to solve the engineering challenges that the designers face everyday. For this project, you must work in teams of two students. Please see me if you canโt find a partner. The processor you will be designing is a 32-bit version of the MIPS processor, however the instruction set will be a small subset of the actual MIPS ISA. You should implement the multicycle datapath version of the processor utilizing the VHDL hardware descriptive language. You may use any construct within the VHDL language, however, the design must be of your own. Copying of any form from any source is illegal and will not be accepted under any circumstances. Your new processor supports three instruction formats: R-format, I-format, and J-format as described in the text book and lectures. Table 1 summarizes a minimum set of instructions for your ISA. You may add more instructions for extra credit. Your memories should be word addressed where each word is 32 bits.
2 Implementation Details
Normally, your first goal should be to get the entire instruction set implemented and tested. The best way to accomplish this is to implement the datapath first
Table 1: Required MIPS Instruction Set OpCode [31 : 26]
Function Field [5 : 0] Instruction^ Operation 100011 โโ lw lw $1, 100($2) 101011 โโ sw sw $1, 100($2) 000000 100000 add add $1, $2, $ 000000 100010 sub sub $1, $2, $ 000000 100100 and and $1, $2, $ 000000 100101 or or $1, $2, $ 000000 101010 slt slt $1, $2, $ 000010 โโ j j 100 000100 โโ beq beq $1, $2, 100 000000 100111 nor nor $1, $2, $ 000101 โโ bne bne $1, $2, 100 001000 โโ addi addi $1, $2, 100 001100 โโ andi andi $1, $2, 100 001101 โโ ori ori $1, $2, 100 000000 000010 srl srl $s2,$s0, 000000 000000 sll sll $t1,$s2, 001111 100000 lui lui $t0, 000000 001000 jr jr $ 000011 โโ jal jal 100
without the memory and control interface. Once the datapath is assembled write a testbench or simulation script to test each instruction. If you work with abstraction in mind by first testing each lower-level part completely, it will eliminate potential errors within your design later. Table 1 shows the ISA subset that your CPU should support. The implemen- tation for instructions LW, SW, BEQ, ADD, SUB, AND, OR, SLT, J were already described in the multicycle datapath implementation of the text book. You are responsible for designing the datapath and control logic additions/modifications for the rest of the ISA; i.e., NOR, BNE, ADDI, ANDI, ORI, SRL, SLL, LUI, JR, JAL.
Datapath components: ALU implementation can be done similar to the example described in the book. You can start with a 1-bit ALU cell and construct a 32-bit ALU unit. Note that you may have to modify the existing 1-bit ALU cell design to provide more functions due to the extended ISA in your CPU design. For shift operations,you may implement a separate shifter unit besides ALU. Barrel shifter structures can be used for implementing both left and right shift operations. Barrel shifters are built using multiple levels of 2-1 multiplexer blocks. Figure 1 shows 8-bit left shifter. Same unit can be used for right shift operation with a slight
lectual Property or other publicly-available code for the datpath and control may be used.
- You are not required to get area and delay numbers for your project, however, you should be able to determine the critical path for the cycle time by making some assumptions. This should be noted in your project report.
- Other parts of the MIPS ISA can be added for extra credit. It is highly recommended you get the baseline design first and tackle extra credit only after you completely test and document the baseline design.
- The datapath handles 32-bit numbers.
- The base datapath is shown in Figure 3 for your reference, however, it is also available in your text as well (i.e. Figure 5.28, page 323). You will modify this datapath in order to extend the instruction subset.
- The control logic should probably be very similar to the multi-cycle control logic described in Chapter 5. The state diagram of the control logic can be found in your text in Figure 5.38. However, you need to expand this state diagram for the additional instructions.
3 Report
Each team will also be required to turn in a report that describes their design. The report should be typed, well written, and well organized. The following items should be included in the report:
- An overview of your design
- Please use the report guideline available at the course web page to understand what sections are required for the final report.
- A discussion of how you tried to optimize your design
- A discussion on any improvements or additional features made to your design
- A discussion of what does not work correctly in your design
- An overview block diagram of your design. In order to draw this appropriately, you will have to understand the multi-cycle MIPS code and its operation.
- A sample simulation of your design that is annotated to show its correct op- eration. You can demo your project to me in person for extra credit.
- Screen-shots should not be used. All output should be printed or captured with other programs. Screen-shots waste printer ink and are non-professional.
Readregister 1Readregister 2WriteregisterWritedata
Registers
ALU
Zero
Readdata 1 Readdata 2
Signextend
16
32
Instruction
[31โ26] Instruction
[25โ21] Instruction
[20โ16] Instruction
[15โ0]
ALUresult
Mux
Mux
Shiftleft 2
Shiftleft 2
Instructionregister
PC
0 1
0^ Mux (^10) Mux 1
0^ Mux 1
A B^
0 1 2 3
0^ M 1 ux 2
ALUOut
Instruction
[15โ0] Memorydataregister
Address^ Memory^ MemDataWritedata
4
Instruction[15โ11]
PCWriteCond
PCWrite
IorD MemReadMemWriteMemtoReg
IRWrite
PCSourceALUOpALUSrcBALUSrcARegWriteRegDst
26
28
Outputs^ Control
Op[5โ0]
PC [31โ28]^ ALUcontrol
Instruction [25-0]
Instruction [5โ0]
Jumpaddress[31โ0]
Figure 3: Multicycle Datapath
